MODEL-SPECIFIC REGISTERS Release 55 Last change 28sep97 Copyright (c) 1996,1997 Ralf Brown ----------S00000000-------------------------- MSR 00000000h - Pentium, Pentium Pro - MACHINE CHECK EXCEPTION ADDRESS Size: 32-36 bits Access: Read Desc: on any Machine Check exception (INT 12), this MSR contains the physical address at which the exception occurred Note: also supported by AMD Am5k86, K5, and K6 SeeAlso: MSR 00000001h,MSR 80000000h,INT 12"MACHINE CHECK" ----------S00000001-------------------------- MSR 00000001h - Pentium, Pentium Pro - MACHINE CHECK EXCEPTION TYPE Size: 6 bits Access: Read Desc: when a Machine Check exception occurs, this register contains the reason for the exception Note: also supported by AMD Am5k86, K5, and K6 SeeAlso: MSR 00000000h,MSR 80000001h,INT 12"MACHINE CHECK" Bitfields for Machine Check Exception type (MSR 00000001h): Bit(s) Description (Table R001) 63-6 reserved (0) 5 "FERI" Fan Error Indicator (Pentium OverDrive only) -- CPU overheated 4 bus cycle causing exception was locked 3 state of M/IO# pin during bus cycle 2 state of D/C# pin during bus cycle 1 state of W/R# pin during bus cycle 0 Machine Check pending (cleared by reading this MSR) ----------S00000002-------------------------- MSR 00000002h - Pentium - (TR1) PARITY REVERSAL TEST REGISTER Size: 14 bits Access: Write SeeAlso: MSR 00000004h,MSR 80000002h Bitfields for Parity Reversal Test Register (TR1): Bit(s) Description (Table R002) 63-14 reserved (0) 13 microcode 12 Data TLB data 11 Data TLB tag 10 Data Cache data 9 Data Cache tag 8 Code TLB data 7 Code TLB tag 6 "ID3" data cache odd bits 129-255 5 "ID2" data cache even bits 128-254 4 "ID1" data cache odd bits 1-127 3 "ID0" data cache even bits 0-126 2 instruction cache tag 1 do not go into SHUTDOWN mode on parity error 0 (read/write-clear) "Parity Error Summary" set on any parity error Note: bits 2-13 indicate that the parity should be reversed for the given subsystem, thus always forcing a parity error ----------S00000003-------------------------- MSR 00000003h - Pentium - INVALID Note: attempted accesses to this MSR cause an exception SeeAlso: MSR 80000003h,MSR 0000000Fh ----------S00000004-------------------------- MSR 00000004h - Pentium - (TR2) INSTRUCTION CACHE END BITS Size: 4 bits Access: Read/Write Note: documented as reserved on Pentium MMX SeeAlso: MSR 00000002h,MSR 00000005h,MSR 80000004h Bitfields for Instruction Cache End Bits (TR2): Bit(s) Description (Table R003) 63-4 reserved (0) 3-0 end bits SeeAlso: #R004 ----------S00000005-------------------------- MSR 00000005h - Pentium - (TR3) CACHE DATA TEST REGISTER Size: 32 bits Access: Read/Write SeeAlso: MSR 00000004h,MSR 00000006h,MSR 80000005h Bitfields for Cache Data Test Register (TR3): Bit(s) Description (Table R004) 63-32 reserved (0) 31-0 data read/written from/to cache (code or data) SeeAlso: #R005 ----------S00000006-------------------------- MSR 00000006h - Pentium - (TR4) CACHE TAG Size: 32 bits Access: Read/Write SeeAlso: MSR 00000005h,MSR 00000007h,MSR 80000006h Bitfields for Cache Tag Test Register (TR4): Bit(s) Description (Table R005) 63-32 reserved (0) 31-8 cache tag (bits 35-12 of address) 8-3 reserved (0) 2 LRU (P54C) =0 Way 0 =1 Way 1 4-2 LRU (P55C [PentiumMMX]) =X00 Way 0 =X10 Way 1 =0X1 Way 2 =1X1 Way 3 1-0 Valid ---code cache (selected by TR5)--- x0 cache line invalid x1 cache line valid ---data cache (selected by TR5)--- 00 cache line invalid 01 cache line shared 10 cache line exclusive 11 cache line modified SeeAlso: #R004,#R006 ----------S00000007-------------------------- MSR 00000007h - Pentium - (TR5) CACHE CONTROL Size: 15 bits Access: Write SeeAlso: MSR 00000006h,MSR 00000008h,MSR 80000007h Bitfields for Cache Control Test Register (TR5): Bit(s) Description (Table R006) 63-20 reserved (0) 19 entry[1] (PentiumMMX only) combined with bit 12, selects Way within cache set 18-15 reserved (0) 14 cache write-back mode (instead of write-through) enabled 13 select data cache instead of code cache 12 select Way within cache set 11-5 cache set number 4-2 buffer select (specify which 32-bit portion of cache line to access) 1-0 control 00 normal operation 01 test write 10 test read 11 flush (action controlled by TR7) SeeAlso: #R004,#R005 ----------S00000008-------------------------- MSR 00000008h - Pentium - (TR6) TLB COMMAND Size: 32 bits Access: Read/Write SeeAlso: MSR 00000007h,MSR 00000009h,MSR 80000008h Bitfields for Pentium TLB Command Test Register: Bit(s) Description (Table R007) 63-32 reserved (0) 31-12 linear address 11 TLB entry is valid 10 page is dirty (has been written to) 9 page may only be accessed from Ring 0 8 page may be written 7-3 reserved (0) 2 page is 4M instead of 4K 1 data TLB instead of code TLB 0 operation (0=write, 1=read) SeeAlso: #R008 ----------S00000009-------------------------- MSR 00000009h - Pentium - (TR7) TLB DATA Size: 32 bits Access: Read/Write SeeAlso: MSR 00000008h,MSR 0000000Bh,MSR 80000009h Bitfields for Pentium TLB Data Test Register (TR7): Bit(s) Description (Table R008) 63-32 reserved (0) 31-12 physical address 11 Page Cache Disable 10 Page Write-Through 9-7 TLB Least-Recently Used value (non-MMX Pentium only) 6-5 reserved (0) (P54C) 6-5 bits 5-4 of TLB entry number (PentiumMMX only) 4 Hit Indicator 3-0 bits 3-0 of TLB entry number (PentiumMMX only) 3-2 TLB entry number (non-MMX Pentium) 1-0 reserved (0) (non-MMX Pentium) Note: if a write with bit 4 (Hit Indicator) set is followed by a read, the value returned in bit 4 indicates whether the selected address was found in the TLB; if found, bits 3-2 indicate which entry contained the hit SeeAlso: #R007,#R009 ----------S0000000A-------------------------- MSR 0000000Ah O - Pentium A-step - (TR8) 36-BIT TLB DATA TEST REGISTER Size: 4 bits Note: attempted accesses to this MSR cause an exception on any Pentium except A-step chips, since the 36-bit physical addressing feature was removed from the Pentium prior to general release SeeAlso: MSR 8000000Ah Bitfields for Pentium A-step 36-bit addressing Test Register (TR8): Bit(s) Description (Table R009) 63-4 reserved (0) 3-0 high bits of physical address (A35-A32) SeeAlso: #R008 ----------S0000000B-------------------------- MSR 0000000Bh - Pentium - (TR9) BRANCH TARGET BUFFER TAG Size: 32 bits Access: Read/Write SeeAlso: MSR 00000009h,MSR 0000000Ch,MSR 8000000Bh Bitfields for non-MMX Pentium Branch Target Buffer Tag (TR9): Bit(s) Description (Table R010) 63-32 reserved (0) 31-6 tag address (bits 31-6 of last byte of branch) 5-2 reserved (0) 1-0 history (state of current branch) SeeAlso: #R012,#R013,#R011 Bitfields for PentiumMMX Branch Target Buffer Tag (TR9): Bit(s) Description (Table R011) 63-32 reserved 31-8 tag address (bits 31-8 of last byte of branch) 7-6 offset (bits 1-0 of last byte of branch) 5 valid BTB entry 4 predicted as taken 3-0 history (state of current branch) SeeAlso: #R010 ----------S0000000C-------------------------- MSR 0000000Ch - Pentium - (TR10) BRANCH TARGET BUFFER TARGET Size: 32 bits Access: Read/Write SeeAlso: MSR 0000000Bh,MSR 0000000Dh,MSR 8000000Ch Bitfields for Pentium Branch Target Buffer Target (TR10): Bit(s) Description (Table R012) 63-32 reserved (0) 31-0 target address SeeAlso: #R010,#R013 ----------S0000000D-------------------------- MSR 0000000Dh - Pentium - (TR11) BRANCH TARGET BUFFER CONTROL Size: 12 bits Access: Write SeeAlso: MSR 0000000Ch,MSR 0000000Eh,MSR 8000000Dh Bitfields for Pentium Branch Target Buffer Control (TR11): Bit(s) Description (Table R013) 63-26 reserved (0) 25-24 branch type (PentiumMMX only) 00 conditional branch 01 unconditional jump 10 call 11 return 23-13 reserved (0) 12 bit 2 of test command (PentiumMMX only) 11-8 BTB set number to access (non-MMX) 11-8 BTB set number to access (PentiumMMX only) 7-6 BTB bank (PentiumMMX only) 5-4 reserved (0) 3-2 BTB entry (way) within set 1-0 test command 00 normal operation 01 test write 10 test read 11 flush 101 test read tag (PentiumMMX only) SeeAlso: #R010,#R012 ----------S0000000E-------------------------- MSR 0000000Eh - Pentium - (TR12) NEW FEATURE CONTROL Size: 10 bits Access: Write SeeAlso: MSR 0000000Dh,MSR 8000000Eh Bitfields for Pentium New Feature Control (TR12): Bit(s) Description (Table R014) 63-21 reserved (0) 20 (PentiumMMX only) Data Cache Inhibit (disable internal data cache) 19 (PentiumMMX only) Code Cache Inhibit (disable internal code cache) 18-10 reserved (0) 9 enable I/O instruction restart for SMM and use different interrupt priority 8 generate fast branch-trace message bus cycles 7 ??? (documented as reserved) 6 disable auto-halt feature (P54C only) 5 ??? (documented as reserved) 4 disable internal APIC 3 Cache Inhibit (disable internal L1 cache) 2 Single-Pipe Execution (disable V pipeline) 1 enable special branch trace message cycle on BTB hit (default = 0) 0 disable branch prediction (no BTB) ----------S0000000F-------------------------- MSR 0000000Fh - Pentium - INVALID Note: attempted accesses to this MSR cause an exception SeeAlso: MSR 8000000Fh,MSR 00000003h ----------S00000010-------------------------- MSR 00000010h - Pentium, Pentium Pro - TIME STAMP COUNTER REGISTER Size: 64 bits Access: Read/Write Note: on a Pentium Pro, only the low 32 bits may be written; on writes, the high 32 bits are cleared to 00000000h SeeAlso: MSR 80000010h ----------S00000011-------------------------- MSR 00000011h - Pentium - EVENT COUNTER SELECTION AND CONTROL Size: 26 bits Access: Read/Write SeeAlso: MSR 00000012h,MSR 00000013h,MSR 00000186h,MSR 80000011h Bitfields for Pentium Event Counter Control: Bit(s) Description (Table R015) 63-27 reserved (0) 26 (Cyrix 6x86MX only) "ES1" bit 6 of event type for counter 1 25 external pin PM1 shows counter overflows instead of counter increments 24 counter 1 counts clock cycles instead of events 23 enable counter 1 counting in CPL3 22 enable counter 1 counting in CPL2-0 21-16 event type for counter 1 (see #R016) 15-11 reserved 10 (Cyrix 6x86MX only) "ES0" bit 6 of event type for counter 0 9 external pin PM0 shows counter overflows instead of counter increments 8 counter 0 counts clock cycles instead of events 7 enable counter 0 counting in CPL3 6 enable counter 0 counting in CPL2-0 5-0 event type for counter 0 (see #R016) (Table R016) Values for Pentium/6x86MX Event Counter event type: 00h data read 01h data write 02h data TLB miss 03h data read miss 04h data write miss 05h write hit to Modified/Exclusive cache line 06h data cache lines written back 07h external data cache snoops 08h external data cache snoop hits 09h simultaneous memory accesses in both pipes 0Ah data bank access conflict between U and V pipes 0Bh misaligned data memory or I/O references 0Ch code read 0Dh code TLB miss 0Eh code cache miss 0Fh any segment register load 10h (Pentium only) segment descriptor cache accessed 11h (Pentium only) segment descriptor cache hit 12h any branch 13h BTB hit 14h taken branch / BTB hit 15h pipeline flushes 16h total instructions executed 17h instruction executed in V pipe 18h bus utilization 19h pipeline stalled by write backups 1Ah pipeline stalled by data memory read 1Bh pipeline stalled by write to Modified/Exclusive cache line 1Ch locked bus cycle 1Dh I/O cycle 1Eh non-cacheable memory references 1Fh pipeline stalled by Address Generation Interlock 20h reserved 21h reserved 22h floating-point operations 23h Breakpoint 0 match 24h Breakpoint 1 match 25h Breakpoint 2 match 26h Breakpoint 3 match 27h hardware interrupt 28h data read or data write 29h data read/write miss ---Pentium--- 2Ah-3Fh reserved ---PentiumMMX--- 2Ah bus ownership latency (counter 0, duration) or bus ownership transfers (counter 1) 2Bh MMX instructions executed in U pipe (counter 0) or V pipe (counter 1) 2Ch cache M-state line sharing (counter 0) or cache line sharing (counter 1) 2Dh EMMS instructions executed (counter 0) or transitions between MMX/FP (counter 1) 2Eh bus use due to processor activity (counter 0, duration) or writes to non-cacheable memory (counter 1) 2Fh saturating MMX instructions executed (counter 0) or saturations performed (counter 1) 30h number of cycles not in HLT state (counter 0) or number of cycles in HLT state (counter 1) 31h MMX instruction data reads (counter 0) or MMX instruction data read misses 32h floating-point stalls (counter 0) or taken branches (counter 1) 33h D1 starvation and FIFO is empty (counter 0) or D1 starvation and only one instruction in FIFO (counter 1) 34h MMX instruction data writes (counter 0) or MMX instruction data write misses (counter 1) 35h pipeline flushes due to wrong branch prediction (counter 0) or pl. flushes due to wrong branch pred. resolved in WB stage (counter 1) 36h misaligned data memory reference on MMX instruction (counter 0) or pipeline stalled waiting for MMX instruction data mem read (counter 1) 37h returns, predicted incorrectly or not at all (counter 0) or total returns predicted (counter 1) 38h clocks MMX instruction multiply unit interlock (counter 0) or clocks MOVD/MOVQ store stall (counter 1) 39h returns (counter 0 only) 3Ah BTB false entries (counter 0) or BTB prediction miss on not-taken branch (counter 1) 3Bh clocks MMX instruction stalled due to full write buffers (counter 0) or clocks stalled on MMX instruction write to E or M line (counter 1) ---6x86MX--- 2Ah reserved 2Bh MMX instructions executed in X pipe (counter 0) or Y pipe (counter 1) 2Ch reserved 2Dh EMMS instructions executed (counter 0) or transitions between MMX/FP (counter 1) 2Eh reserved 2Fh saturating MMX instructions executed (counter 0) or saturations performed (counter 1) 30h reserved 31h MMX instruction data reads (counter 0 only) 32h taken branches (counter 1 only) 33h-36h reserved 37h returns, predicted incorrectly or not at all (counter 0) or total returns predicted (counter 1) 38h clocks MMX instruction multiply unit interlock (counter 0) or clocks MOVD/MOVQ store stall (counter 1) 39h returns (counter 0) or return stack buffer overflows (counter 1) 3Ah BTB false entries (counter 0) or BTB prediction miss on not-taken branch (counter 1) 3Bh clocks MMX instruction stalled due to full write buffers (counter 0) or clocks stalled on MMX instruction write to E or M line (counter 1) 3Ch-3Fh reserved 40h L2 TLB misses (code or data) 41h L2 TLB data miss 42h L2 TLB code miss 43h L1 TLB miss (code or data) 44h TLB flushes 45h TLB page invalidations 46h TLB page invalidations which hit 47h reserved 48h instructions decoded 49h-7Fh reserved SeeAlso: #R015 ----------S00000012-------------------------- MSR 00000012h - Pentium - EVENT COUNTER #0 Size: 40 bits Access: Read/Write SeeAlso: MSR 00000011h,MSR 00000013h,MSR 80000012h,MSR 000000C1h ----------S00000013-------------------------- MSR 00000013h - Pentium - EVENT COUNTER #1 Size: 40 bits Access: Read/Write SeeAlso: MSR 00000011h,MSR 00000012h,MSR 80000013h,MSR 000000C2h ----------S00000014-------------------------- MSR 00000014h - Pentium P54C - bug? Note: returns 0 on all reads and ignores any writes for P54C processors with CPUID values <= 0524h, rather than causing an exception; possibly due to a microcode bug ----------S0000001B-------------------------- MSR 0000001Bh - Pentium Pro - APIC BASE ADDRESS SeeAlso: MEM FEE00000h Bitfields for Pentium Pro MSR 0000001Bh: Bit(s) Description (Table R017) 63-12 ??? 11 APIC global enable (can not be cleared except through hard reset) 10-9 reserved 8 BootStrap Processor 7-0 ??? ----------S0000002A-------------------------- MSR 0000002Ah - Pentium Pro - "EBL_CR_POWERON" Size: 32 bits Access: Read/write Bitfields for Pentium Pro MSR 0000002Ah: Bit(s) Description (Table R018) 0 data bus uses ECC instead of parity 1 disable data error checking 2 disable response error checking 3 disable AERR# drive 4 disable BERR# for initiator bus requests 6 disable BERR# for initiator internal errors 7 disable BINIT# drive 8 output tri-state enabled 9 Execute-BIST enabled 10 (read-only) AERR# observation enabled 12 (read-only) BINIT# observation enabled 13 (read-only) IN Order Queue depth is 1 instead of 8 14 (read-only) Power-on Reset Vector at 1M instead of 4G 15 (read-only) FRC mode enabled 17-16 (read-only) APIC cluster ID 19-18 ??? 21-20 (read-only) symmetric arbitration ID 24-22 (read-only) clock frequency ratio 25 reserved 26 (read-only) Low Power enable 31-27 reserved ----------S00000032-------------------------- MSR 00000032h - Pentium Pro - ??? ----------S00000033-------------------------- MSR 00000033h - Pentium Pro - ??? Bitfields for Pentium Pro MSR 0033h: Bit(s) Description (Table R019) 31 (step sB1 and later) disable LOCK# for locked transactions which are split across a cache line boundary 30 (step sB1 and later) disable Instruction Streaming buffers --used to work around sB1 errata 58 and 59 29-0 ??? ----------S00000034-------------------------- MSR 00000034h - Pentium Pro - ??? ----------S0000003A-------------------------- MSR 0000003Ah - Pentium Pro - ??? ----------S00000050-------------------------- MSR 00000050h - Pentium Pro - ??? ----------S00000051-------------------------- MSR 00000051h - Pentium Pro - ??? ----------S00000052-------------------------- MSR 00000052h - Pentium Pro - ??? ----------S00000053-------------------------- MSR 00000053h - Pentium Pro - ??? ----------S00000054-------------------------- MSR 00000054h - Pentium Pro - ??? ----------S00000079-------------------------- MSR 00000079h - Pentium Pro - BIOS UPDATE TRIGGER Size: 32 bits Access: Write Desc: writing the linear address of a microcode update block (see #0457) to this MSR cause the CPU to initiate a microcode load SeeAlso: INT 15/AX=D042h/BL=01h,MSR 0000008Bh ----------S00000082-------------------------- MSR 00000082h - AMD Am5k86 (AMD-K5) - ARRAY ACCESS REGISTER Size: 64 bits Note: EDX remains unchanged after an RDMSR to simplify multiple accesses SeeAlso: MSR 00000083h Bitfields for AMD Am5k86 (AMD-K5) Array Access Register: Bit(s) Description (Table R020) 63-40 pointer within array specified below 39-32 array identifier (see #R021) 31-0 array data SeeAlso: #R033 (Table R021) Values for AMD Am5k86 Array Pointer: E0h data cache (data) E1h data cache (linear tag) (see #R022) E4h code cache (instruction) (see #R023) E5h code cache (linear tag) (see #R024) E6h code cache (valid bits) (see #R025) E7h code cache (branch-prediction bits) (see #R026) E8h 4K TLB (page) (see #R027) E9h 4K TLB (linear tag) (see #R028) EAh 4M TLB (page) (see #R029) EBh 4M TLB (linear tag) (see #R030) ECh data cache (physical tag) (see #R031) EDh code cache (physical tag) (see #R032) SeeAlso: #R020 Bitfields for AMD AmK586 data cache linear tag: Bit(s) Description (Table R022) 31-26 reserved (0) 25 cache line is dirty 24 user/supervisor 23 read/write 22 0 21 linear address valid 20-0 tag SeeAlso: #R021,#R031 Bitfields for AMD Am5k86 code cache instruction: Bit(s) Description (Table R023) 31-26 reserved (0) 25 start bit 1 24 end bit 1 23 opcode bit 1 22-21 map (ROPs/MROM) 1 20-13 byte 1 12 start bit 0 11 end bit 0 10 opcode bit 0 9-8 map (ROPs/MROM) 0 7-0 byte 0 SeeAlso: #R021,#R024,#R032 Bitfields for Am5k86 code cache linear tag: Bit(s) Description (Table R024) 31-20 reserved (0) 19-0 bits 31-12 of linear address SeeAlso: #R021,#R023,#R025,#R032 Bitfields for Am5k86 code cache valid bits: Bit(s) Description (Table R025) 31-18 reserved (0) 17 linear tag is valid 16 user/supervisor 15-0 bitmask of valid bytes SeeAlso: #R021,#R023,#R032 Bitfields for Am5k86 code cache branch prediction bits: Bit(s) Description (Table R026) 31-19 reserved (0) 18 predicted branch taken 17-14 offset of last byte of predicted branch instruction within block 13-12 predicted target column 11-4 predicted target index 3-0 target byte SeeAlso: #R021 Bitfields for Am5k86 4K TLB page: Bit(s) Description (Table R027) 31-22 reserved (0) 21 page cache disable 20 page write-through 19-0 page frame address SeeAlso: #R021,#R028,#R029 Bitfields for Am5k86 4K TLB linear tag: Bit(s) Description (Table R028) 31-20 reserved (0) 19 global valid bit 18 TLB entry is dirty 17 user/supervisor 16 read/write 15 entry is valid 14-0 tag (bits 31-17 of address) SeeAlso: #R021,#R027,#R030 Bitfields for Am5k86 4M TLB page: Bit(s) Description (Table R029) 31-12 reserved (0) 11 page cache disable 10 page write-through 9-0 page frame address SeeAlso: #R021,#R027,#R030 Bitfields for Am5k86 4M TLB linear tag: Bit(s) Description (Table R030) 31-15 reserved (0) 14 global valid bit 13 TLB entry is dirty 12 user/supervisor 11 read/write 10 entry is valid 9-0 tag (bits 31-22 of address) SeeAlso: #R021,#R028,#R029 Bitfields for Am5k86 data cache physical tag: Bit(s) Description (Table R031) 31-23 reserved (0) 22-21 MESI status 00 invalid 01 shared 10 modified 11 exclusive 20-0 tag (bits 31-11 of physical address) SeeAlso: #R021,#R032 Bitfields for Am5k86 code cache physical tag: Bit(s) Description (Table R032) 31-21 reserved (0) 20 valid 19-0 tag (bits 31-12 of physical address) SeeAlso: #R021,#R031 ----------S00000083-------------------------- MSR 00000083h - AMD Am5k86 (AMD-K5) - HARDWARE CONFIGURATION REGISTER Size: 8 bits SeeAlso: MSR 00000082h Bitfields for AMD Am5k86 (AMD-K5) Hardware Configuration Register: Bit(s) Description (Table R033) 63-8 reserved 7 disable data cache 6 disable instruction cache 5 disable branch prediction 4 enable write allocation (stepping 4 and higher only) 3-1 debug control 000 off 001 enable branch trace (requires bit 5 set as well) 100 enable Probe Mode on debug trap other reserved 0 disable Stopping Processor Clock in Halt and Stop Grant states SeeAlso: #R020 ----------S00000085-------------------------- MSR 00000085h - AMD-K5 - WRITE ALLOCATE TOP-OF-MEMORY AND CONTROL REGISTER Note: this MSR is supported on K5 models 1/2/3 stepping 4 and higher only SeeAlso: MSR 00000086h !!!amd\21062e.pdf p.95 ----------S00000086-------------------------- MSR 00000086h - AMD-K5 - WRITE ALLOCATE PROGRAMMABLE MEMORY RANGE REGISTER Note: this MSR is supported on K5 models 1/2/3 stepping 4 and higher only SeeAlso: MSR 00000085h ----------S00000088-------------------------- MSR 00000088h - Pentium Pro - ??? ----------S00000089-------------------------- MSR 00000089h - Pentium Pro - ??? ----------S0000008A-------------------------- MSR 0000008Ah - Pentium Pro - ??? ----------S0000008B-------------------------- MSR 0000008Bh - Pentium Pro - "BIOS_SIGN" BIOS UPDATE SIGNATURE Size: 64 bits Access: Read/Write Desc: used to determine which (if any) microcode update has been loaded into the CPU Notes: whenever a microcode update is loaded, the PentiumPro modifies the operation of the CPUID instruction to store both the standard CPUID model information and a 32-bit microcode update ID into this MSR; if no microcode update has been loaded, the MSR remains unchanged (it is normally cleared to 0 before using CPUID to test for updates) the low 32 bits of this register (if modified by CPUID) contains the standard model/stepping information, while the high 32 bits contain the microcode update ID SeeAlso: MSR 00000079h ----------S000000AE-------------------------- MSR 000000AEh - Pentium Pro - ??? ----------S000000C1-------------------------- MSR 000000C1h - Pentium Pro - "PERFCTR0" PERFORMANCE COUNTER REGISTER 0 Note: the performance measure counted by this MSR is set through MSR 0186h SeeAlso: MSR 000000C2h,MSR 00000012h,MSR 00000186h ----------S000000C2-------------------------- MSR 000000C2h - Pentium Pro - "PERFCTR1" PERFORMANCE COUNTER REGISTER 1 Note: the performance measure counted by this MSR is set through MSR 0187h SeeAlso: MSR 000000C1h,MSR 00000013h,MSR 00000187h ----------S000000FE-------------------------- MSR 000000FEh - Pentium Pro - "MTRRcap" MEMORY TYPE RANGE REGISTER CAPABILITIES Desc: determine how many and what type of Memory Type Range Registers are implemented SeeAlso: MSR 00000200h,MSR 00000250h,MSR 000002FFh ----------S00000116-------------------------- MSR 00000116h - Pentium Pro - ??? ----------S00000118-------------------------- MSR 00000118h - Pentium Pro - ??? ----------S00000119-------------------------- MSR 00000119h - Pentium Pro - ??? ----------S0000011B-------------------------- MSR 0000011Bh - Pentium Pro - ??? ----------S00000131-------------------------- MSR 00000131h - Pentium Pro - ??? ----------S0000014E-------------------------- MSR 0000014Eh - Pentium Pro - ??? ----------S0000014F-------------------------- MSR 0000014Fh - Pentium Pro - ??? ----------S00000150-------------------------- MSR 00000150h - Pentium Pro - ??? ----------S00000151-------------------------- MSR 00000151h - Pentium Pro - ??? ----------S00000154-------------------------- MSR 00000154h - Pentium Pro - ??? ----------S0000015B-------------------------- MSR 0000015Bh - Pentium Pro - ??? ----------S0000015F-------------------------- MSR 0000015Fh - Pentium Pro - ??? ----------S00000174-------------------------- MSR 00000174h - Pentium Pro - ??? ----------S00000175-------------------------- MSR 00000175h - Pentium Pro - ??? ----------S00000176-------------------------- MSR 00000176h - Pentium Pro - ??? ----------S00000179-------------------------- MSR 00000179h - Pentium Pro - "MCG_CAP" SeeAlso: MSR 0000017Ah,MSR 0000017Bh ----------S0000017A-------------------------- MSR 0000017Ah - Pentium Pro - "MCG_STATUS" SeeAlso: MSR 00000179h,MSR 0000017Bh ----------S0000017B-------------------------- MSR 0000017Bh - Pentium Pro - "MCG_CTL" SeeAlso: MSR 00000179h,MSR 0000017Ah ----------S00000186-------------------------- MSR 00000186h - Pentium Pro - "EVNTSEL0" - PERFORM. COUNTER EVENT SELECTION 0 Size: 32 bits Access: Read/Write SeeAlso: MSR 000000C1h,MSR 00000187h,MSR 00000011h,MSR 00000012h Bitfields for Pentium Pro Event Selection MSR: Bit(s) Description (Table R034) 7-0 event type (see #R035) 15-8 UMASK (Unit Mask register; set to 0 to enable all count options) 16 USER (enable counting in rings 1,2,3) 17 OS (enable counting in ring 0) 18 count occurrences, not duration 19 signal performance counter overflows via BP0/BP1 pin 20 signal performance counter overflows via APIC input 22 enable counting of events 23 invert result of CMASK condition 31-24 CMASK (counter mask) (Table R035) Values for Pentium Pro/Pentium II performance event type: 00h-02h documented as unused 03h number of store buffer blocks 04h number of store buffer drain cycles 05h misaligned data memory references 06h segment register loads 07h-0Fh documented as unused 10h executed computational FLOPS 11h microcode handled FP exceptions 12h number of multiplies 13h number of divisions 14h divider busy cycles 15h-20h documented as unused 21h address strobes 22h data bus wait cycles 23h data bus transfer cycles 24h allocated L2-cache lines 25h allocated L2 modified lines 26h removed L2 lines 27h removed modified L2 lines 28h instruction fetches 29h loads 2Ah stores 2Bh-2Dh documented as unused 2Eh L2 requests 2Fh-42h documented as unused 43h L1 memory references 44h documented as unused 45h L1 allocated lines 46h L1 allocated M-state lines 47h L1 evicted M-state lines 48h L1 outstanding miss cycles (weighted) 49h-51h documented as unused 52h (P-II) self-modifying code occurrences 53h-5Fh documented as unused 60h outstanding bus requests 61h BNR driven cycles 62h DRDY asserted cycles 63h number of cycles with LOCK asserted 64h CPU receiving data cycles 65h burst-read transactions 66h read for ownership transactions 67h write-back transactions 68h instruction-fetch transactions 69h invalidate transactions 6Ah partial-write transactions 6Bh partial transactions 6Ch I/O transactions 6Dh deferred transactions 6Eh burst transactions 6Fh memory transactions 70h total of all transactions 71h-78h documented as unused 79h processor not-halted cycles 7Ah HIT driven cycles 7Bh HITM driven cycles 7Ch-7Dh documented as unused 7Eh bus-snoop stall cycles 7Fh documented as unused 80h instruction fetches 81h instruction fetch misses 82h-84h documented as unused 85h iTLB misses 86h instruction-fetch stall cycles 87h instruction-length decoder stall cycles 88h-A1h documented as unused A2h resource-related stall cycles A3h-AFh documented as unused B0h (P-II) MMX instructions executed B1h (P-II) saturated arithmetic instructions executed B2h (P-II) MMX uOPs executed on Port #0--3 B3h (P-II) MMX instructins B4h-BFh documented as unused C0h retired instructions C1h retired FLOPs C2h retired uOPs C3h documented as unused C4h retired branch predictions C5h retired mispredicted branches C6h total cycles with interrupts disabled C7h disabled interrupts pending cycles C8h received hardware interrupts C9h retired taken branches CAh retired taken mispredicted branches CBh documented as unused CCh (P-II) transitions between FP and MMX states CDh (P-II) SIMD assists (EMMS instructions executed) CEh (P-II) MMX instructions retired CFh (P-II) saturated arithmetic instructions retired D0h decoded instructions D1h documented as unused D2h partial stall cycles or events D3h documented as unused D4h (P-II) segment rename stalls D5h (P-II) segment renames D6h (P-II) retired segment renames D7h-DFh documented as unused E0h decoded branch instructinos E1h documented as unused E2h BTB misses E3h documented as unused E4h bogus branches E5h documented as unused E6h BACLEAR asserted E7h-FFh documented as unused ----------S00000187-------------------------- MSR 00000187h - Pentium Pro - "EVNTSEL1" - PERFORM. COUNTER EVENT SELECTION 1 Size: 32 bits Access: Read/Write SeeAlso: MSR 000000C2h,MSR 00000186h,#R034,MSR 00000011h,MSR 00000013h ----------S000001D3-------------------------- MSR 000001D3h - Pentium Pro - ??? ----------S000001D9-------------------------- MSR 000001D9h - Pentium Pro - "DEBUGCTLMSR" DEBUGGING CONTROL Bitfields for Pentium Pro Debugging Control MSR: Bit(s) Description (Table R036) 0 enable Last Branch records (see MSR 000001DBh,MSR 000001DCh) 1 Branch Trap Flag 2 performance monitor/Breakpoint pins 3 performance monitor/Breakpoint pins 4 performance monitor/Breakpoint pins 5 performance monitor/Breakpoint pins 6 enable execution trace messages 13-7 reserved 14 enable execution trace messages 15 enable execution trace messages ----------S000001DB-------------------------- MSR 000001DBh - Pentium Pro - "LASTBRANCHFROMIP" Desc: stores the address from which a branch was last taken SeeAlso: MSR 000001DCh,MSR 000001DDh ----------S000001DC-------------------------- MSR 000001DCh - Pentium Pro - "LASTBRANCHTOIP" Desc: stores the destination address of the last taken branch instruction SeeAlso: MSR 000001DBh,MSR 000001DEh ----------S000001DD-------------------------- MSR 000001DDh - Pentium Pro - "LASTINTFROMIP" Desc: stores the address at which an interrupt last occurred SeeAlso: MSR 000001DBh,MSR 000001DEh ----------S000001DE-------------------------- MSR 000001DEh - Pentium Pro - "LASTINTTOIP" Desc: stores the address to which the last interrupt caused a branch SeeAlso: MSR 000001DCh,MSR 000001DDh ----------S000001E0-------------------------- MSR 000001E0h - Pentium Pro - "ROB_CR_BKUPTMPDR6" Size: >= 3 bits Bitfields for Pentium Pro MSR 000001E0h: Bit(s) Description (Table R037) 63-3 ??? 2 Fast String Enable (default is enabled) 1-0 reserved Note: if bit 2 is set, REP MOVS moves 64 bits each clock cycle ----------S00000200-------------------------- MSR 00000200h - Pentium Pro - "MTRRphysBase0" SeeAlso: MSR 000000FEh,MSR 00000201h,MSR 00000202h ----------S00000201-------------------------- MSR 00000201h - Pentium Pro - "MTRRphysMask0" SeeAlso: MSR 000000FEh,MSR 00000200h,MSR 00000202h ----------S00000202-------------------------- MSR 00000202h - Pentium Pro - "MTRRphysBase1" SeeAlso: MSR 000000FEh,MSR 00000200h,MSR 00000203h ----------S00000203-------------------------- MSR 00000203h - Pentium Pro - "MTRRphysMask1" SeeAlso: MSR 000000FEh,MSR 00000201h,MSR 00000202h ----------S00000204-------------------------- MSR 00000204h - Pentium Pro - "MTRRphysBase2" ----------S00000205-------------------------- MSR 00000205h - Pentium Pro - "MTRRphysMask2" ----------S00000206-------------------------- MSR 00000206h - Pentium Pro - "MTRRphysBase3" ----------S00000207-------------------------- MSR 00000207h - Pentium Pro - "MTRRphysMask3" ----------S00000208-------------------------- MSR 00000208h - Pentium Pro - "MTRRphysBase4" ----------S00000209-------------------------- MSR 00000209h - Pentium Pro - "MTRRphysMask4" ----------S0000020A-------------------------- MSR 0000020Ah - Pentium Pro - "MTRRphysBase5" ----------S0000020B-------------------------- MSR 0000020Bh - Pentium Pro - "MTRRphysMask5" ----------S0000020C-------------------------- MSR 0000020Ch - Pentium Pro - "MTRRphysBase6" ----------S0000020D-------------------------- MSR 0000020Dh - Pentium Pro - "MTRRphysMask6" ----------S0000020E-------------------------- MSR 0000020Eh - Pentium Pro - "MTRRphysBase7" ----------S0000020F-------------------------- MSR 0000020Fh - Pentium Pro - "MTRRphysMask7" ----------S00000250-------------------------- MSR 00000250h - Pentium Pro - "MTRRfix64K_00000" SeeAlso: MSR 000000FEh,MSR 00000200h,MSR 00000258h ----------S00000258-------------------------- MSR 00000258h - Pentium Pro - "MTRRfix16K_80000" SeeAlso: MSR 000000FEh,MSR 00000250h,MSR 00000259h ----------S00000259-------------------------- MSR 00000259h - Pentium Pro - "MTRRfix16K_A0000" ----------S00000268-------------------------- MSR 00000268h - Pentium Pro - "MTRRfix4K_C0000" ----------S00000269-------------------------- MSR 00000269h - Pentium Pro - "MTRRfix4K_C8000" ----------S0000026A-------------------------- MSR 0000026Ah - Pentium Pro - "MTRRfix4K_D0000" ----------S0000026B-------------------------- MSR 0000026Bh - Pentium Pro - "MTRRfix4K_D8000" ----------S0000026C-------------------------- MSR 0000026Ch - Pentium Pro - "MTRRfix4K_E0000" ----------S0000026D-------------------------- MSR 0000026Dh - Pentium Pro - "MTRRfix4K_E8000" ----------S0000026E-------------------------- MSR 0000026Eh - Pentium Pro - "MTRRfix4K_F0000" ----------S0000026F-------------------------- MSR 0000026Fh - Pentium Pro - "MTRRfix4K_F8000" ----------S000002FF-------------------------- MSR 000002FFh - Pentium Pro - "MTRRdefType" SeeAlso: MSR 000000FEh,MSR 00000200h,MSR 00000250h Bitfields for Pentium Pro MSR 000002FFh: Bit(s) Description (Table R038) 2-0 default memory type 10 Fixed MTRR enable 11 "MTRRenable" ----------S00000400-------------------------- MSR 00000400h - Pentium Pro - "MC0_CTL" ----------S00000401-------------------------- MSR 00000401h - Pentium Pro - "MC0_STATUS" ----------S00000402-------------------------- MSR 00000402h - Pentium Pro - "MC0_ADDR" ----------S00000403-------------------------- MSR 00000403h - Pentium Pro - "MC0_MISC" ----------S00000404-------------------------- MSR 00000404h - Pentium Pro - "MC1_CTL" ----------S00000405-------------------------- MSR 00000405h - Pentium Pro - "MC1_STATUS" ----------S00000406-------------------------- MSR 00000406h - Pentium Pro - "MC1_ADDR" ----------S00000407-------------------------- MSR 00000407h - Pentium Pro - "MC1_MISC" ----------S00000408-------------------------- MSR 00000408h - Pentium Pro - "MC2_CTL" ----------S00000409-------------------------- MSR 00000409h - Pentium Pro - "MC2_STATUS" ----------S0000040A-------------------------- MSR 0000040Ah - Pentium Pro - "MC2_ADDR" ----------S0000040B-------------------------- MSR 0000040Bh - Pentium Pro - "MC2_MISC" ----------S00001000-------------------------- MSR 00001000h - IBM 386/486 SLC - PROCESSOR OPERATION REGISTER Size: 19 bits Access: Read/Write SeeAlso: MSR 00001001h,MSR 00001002h Bitfields for IBM 386/486 SLC Processor Operation Register: Bit(s) Description (Table R039) 63-19 reserved 18 (486SLC only) Low Power PLA 17 (486SLC only) Bus Read 16 (486SLC only) Cache Parity Generate Error 15 enable cacheability of NPX operands 14 enable PWI ADS 13 enable Low Power Halt Mode (HLT instruction stops CPU clock) 12 extended Out instruction (CPU waits for READY after any output) 11 cache reload bit 10 enable internal KEN# signal 9 disable cache lock mode 8 reserved 7 enable cache 6 enable DBCS 5 enable Power Interrupt 4 enable Flush Snooping 3 enable Snoop Input 2 address line A20 mask (see also #2440,#P121) 1 enable cache parity checking 0 Cache Parity Error occurred SeeAlso: #R040,#R041 ----------S00001000-------------------------- MSR 00001000h - Pentium Pro - DEBUG REGISTER 0 ----------S00001001-------------------------- MSR 00001001h - IBM 386/486 SLC - CACHE REGION CONTROL REGISTER Size: 48 bits SeeAlso: MSR 00001000h,MSR 00001002h Bitfields for IBM 386/486 SLC Cache Region Control Register: Bit(s) Description (Table R040) 63-48 reserved 47-32 extended memory cache memory limit (number of 64K blocks above 1M which may be cached) 31-16 first megabyte read-only flags (each bit represents 64K) 15-0 first megabyte cacheable flags (each bit represents 64K) SeeAlso: #R039,#R041 ----------S00001001-------------------------- MSR 00001001h - Pentium Pro - DEBUG REGISTER 1 ----------S00001002-------------------------- MSR 00001002h - IBM 386/486 SLC - PROCESSOR OPERATION REGISTER Size: 30 bits SeeAlso: MSR 00001000h,MSR 00001001h,MSR 00001004h Bitfields for IBM 386/486 SLC Processor Operation Register: Bit(s) Description (Table R041) 63-30 reserved 29 enable External Dynamic Frequency Shift 28 Dynamic Frequency Shift ready 27 Dynamic Frequency Shift Mode 26-24 clocking mode 000 clock x1 011 clock doubler 100 clock tripler 23-0 reserved SeeAlso: #R039,#R040 ----------S00001002-------------------------- MSR 00001002h - Pentium Pro - DEBUG REGISTER 2 ----------S00001003-------------------------- MSR 00001003h - Pentium Pro - DEBUG REGISTER 3 ----------S00001004-------------------------- MSR 00001004h - IBM 486BL3 - PROCESSOR CONTROL REGISTER Size: 24 bits SeeAlso: MSR 00001000h Bitfields for IBM 486BL3 Processor Control Register: Bit(s) Description (Table R042) 63-24 reserved 23 OS/2 boot (0=DD1 hardware, 1=DD0 hardware) 22 MOV CR0,x Decode 0: DD0, DD1A, DD1B, DD1D hardware 1: DD1C hardware 21 reserved 20 Cache Low Power (DD1 only: cache disabled when not in use) 19 reserved 18 NOP timing 0: 2 cycles on DD0, 3 cycles on DD1 1: 3 cycles on DD0, 2 cycles on DD1 17 bus pipelining for 16-bit accesses 16-5 ??? 4 MOVS split 3 power-saving cache feature 2 reserved 1 enable MOV CRx decode (reserved on DD1B, DD1C) 0 reserved SeeAlso: MSR 00001000h ----------S00001004-------------------------- MSR 00001004h - Pentium Pro - DEBUG REGISTER 4 ----------S00001005-------------------------- MSR 00001005h - Pentium Pro - DEBUG REGISTER 5 ----------S00001006-------------------------- MSR 00001006h - Pentium Pro - DEBUG REGISTER 6 ----------S00001007-------------------------- MSR 00001007h - Pentium Pro - DEBUG REGISTER 7 ----------S00002000-------------------------- MSR 00002000h - Pentium Pro - CONTROL REGISTER 0 ----------S00002002-------------------------- MSR 00002002h - Pentium Pro - CONTROL REGISTER 2 ----------S00002003-------------------------- MSR 00002003h - Pentium Pro - CONTROL REGISTER 3 ----------S00002004-------------------------- MSR 00002004h - Pentium Pro - CONTROL REGISTER 4 ----------S80000000-------------------------- MSR 80000000h - Pentium - MACHINE CHECK EXCEPTION ADDRESS Size: 64 bits Access: Read SeeAlso: MSR 00000000h,MSR 80000001h ----------S80000001-------------------------- MSR 80000001h - Pentium - MACHINE CHECK EXCEPTION TYPE Size: 6 bits Access: Read SeeAlso: MSR 00000001h,MSR 80000000h ----------S80000002-------------------------- MSR 80000002h - Pentium - (TR1) PARITY REVERSAL TEST REGISTER Size: 14 bits Access: Write SeeAlso: MSR 00000002h ----------S80000003-------------------------- MSR 80000003h - Pentium - unimplemented SeeAlso: MSR 00000003h ----------S80000004-------------------------- MSR 80000004h - Pentium - (TR2) INSTRUCTION CACHE END BITS Size: 4 bits Access: Read/Write SeeAlso: MSR 00000004h ----------S80000005-------------------------- MSR 80000005h - Pentium - (TR3) CACHE DATA TEST REGISTER Size: 32 bits Access: Read/Write SeeAlso: MSR 00000005h ----------S80000006-------------------------- MSR 80000006h - Pentium - (TR4) CACHE TAG Size: 32 bits Access: Read/Write SeeAlso: MSR 00000006h ----------S80000007-------------------------- MSR 80000007h - Pentium - (TR5) CACHE CONTROL Size: 15 bits Access: Write SeeAlso: MSR 00000007h ----------S80000008-------------------------- MSR 80000008h - Pentium - (TR6) TLB COMMAND Size: 32 bits Access: Read/Write SeeAlso: MSR 00000008h ----------S80000009-------------------------- MSR 80000009h - Pentium - (TR7) TLB DATA Size: 32 bits Access: Read/Write SeeAlso: MSR 00000009h ----------S8000000A-------------------------- MSR 8000000Ah O - Pentium A-step - (TR8) 36-BIT TLB DATA TEST REGISTER Size: 4 bits SeeAlso: MSR 0000000Ah,#R009 ----------S8000000B-------------------------- MSR 8000000Bh - Pentium - (TR9) BRANCH TARGET BUFFER TAG Size: 32 bits Access: Read/Write SeeAlso: MSR 0000000Bh ----------S8000000C-------------------------- MSR 8000000Ch - Pentium - (TR10) BRANCH TARGET BUFFER TARGET Size: 32 bits Access: Read/Write SeeAlso: MSR 0000000Ch ----------S8000000D-------------------------- MSR 8000000Dh - Pentium - (TR11) BRANCH TARGET BUFFER CONTROL Size: 12 bits Access: Write SeeAlso: MSR 0000000Dh ----------S8000000E-------------------------- MSR 8000000Eh - Pentium - (TR12) NEW FEATURE CONTROL Size: 10 bits Access: Write SeeAlso: MSR 0000000Eh ----------S8000000F-------------------------- MSR 8000000Fh - Pentium - ??? Size: 1 bit??? Access: Write SeeAlso: MSR 0000000Fh ----------S80000010-------------------------- MSR 80000010h - Pentium - TIME STAMP COUNTER Size: 64 bits Access: Read/Write SeeAlso: MSR 00000010h ----------S80000011-------------------------- MSR 80000011h - Pentium - EVENT COUNTER SELECTION AND CONTROL Size: 26 bits Access: Read/Write SeeAlso: MSR 00000011h,MSR 80000012h,MSR 80000013h ----------S80000012-------------------------- MSR 80000012h - Pentium - EVENT COUNTER #0 Size: 40 bits Access: Read/Write SeeAlso: MSR 00000012h,MSR 80000011h,MSR 80000013h ----------S80000013-------------------------- MSR 80000013h - Pentium - EVENT COUNTER #1 Size: 40 bits Access: Read/Write SeeAlso: MSR 00000013h,MSR 80000011h,MSR 80000012h ----------S80000014-------------------------- MSR 80000014h - Pentium - ??? Access: Read SeeAlso: MSR 00000014h ----------S80000015-------------------------- MSR 80000015h - Pentium - unimplemented??? ----------S80000016-------------------------- MSR 80000016h - Pentium - unimplemented??? ----------S80000017-------------------------- MSR 80000017h - Pentium - unimplemented??? ----------S80000018-------------------------- MSR 80000018h - Pentium - ??? (PAGING-RELATED) Size: 4 bits??? Access: Read ----------S80000019-------------------------- MSR 80000019h - Pentium - FLOATING POINT - LAST PREFETCHED OPCODE Size: 11 bits Access: Read Desc: this register stores the opcode of the last floating-point opcode to be prefetched by the CPU SeeAlso: MSR 8000001Ah,MSR 8000001Bh Bitfields for Pentium Floating-Point Opcode: Bit(s) Description (Table R043) 63-11 reserved (0) 10-8 low three bits of first byte of floating-point instruction 7-0 second byte of floating-point instruction Note: both a standalone FWAIT and the instruction D8h 9Bh are represented as 09Bh ----------S8000001A-------------------------- MSR 8000001Ah - Pentium - FLOATING POINT - LAST NON-CONTROL OPCODE Size: 11 bits Access: Read SeeAlso: MSR 80000019h,MSR 8000001Bh,#R043 ----------S8000001B-------------------------- MSR 8000001Bh - Pentium - FLOATING POINT - LAST EXCEPTION OPCODE Size: 11 bits Access: Read/Write SeeAlso: MSR 80000019h,MSR 8000001Ah,#R043 ----------S8000001C-------------------------- MSR 8000001Ch - Pentium - ??? Size: 4 bits??? Access: Read ----------S8000001D-------------------------- MSR 8000001Dh - Pentium - PROBE MODE CONTROL REGISTER Size: 32 bits Access: Read/Write Bitfields for Probe Mode Control Register: Bit(s) Description (Table R044) 31 (read-only) System Management Mode is active 30-3 reserved (0) 2 PB1 monitors breakpoint #1 matches instead of performance counter #1 1 PB0 monitors breakpoint #0 matches instead of performance counter #0 0 ICEBP enabled (every debug exception enters Probe Mode) ----------S8000001E-------------------------- MSR 8000001Eh - Pentium - ??? Size: 32 bits Access: Read/Write Note: this may be nothing more than a scratchpad register SeeAlso: MSR 8000001Fh ----------S8000001F-------------------------- MSR 8000001Fh - Pentium - ??? Size: 32 bits Access: Read/Write Note: this may be nothing more than a scratchpad register SeeAlso: MSR 8000001Eh ----------SC0000080-------------------------- MSR C0000080h - AMD K6 - EXTENDED FEATURE ENABLE REGISTER Size: 1 bit SeeAlso: MSR C0000081h,MSR C0000082h Bitfields for AMD K6 Extended Feature Enable Register: Bit(s) Description (Table R045) 63-1 reserved 0 system call extension (SYSCALL/SYSRET) enabled when disabled, both instructions generate an Undefined Opcode exception Note: CPUID 80000001h should be checked to determine whether the SYSCALL extension is implemented by the processor SeeAlso: #R046 ----------SC0000081-------------------------- MSR C0000081h - AMD K6 - SYSCALL TARGET ADDRESS Size: 48 bits Note: if SYSCALL is supported (as indicated by CPUID; SYSCALL is not yet implemented in current steppings of the K6), this MSR specifies the address to which the SYSCALL instruction (opcode 0Fh 05h -- same as 80286 LOADALL!) transfers control, provided it has also been enabled via MSR C0000080h SeeAlso: MSR C0000080h,MSR C0000082h Bitfields for AMD K6 SYSCALL Target Address Register: Bit(s) Description (Table R046) 63-48 reserved 47-32 CS and SS selector base for SYSCALL/SYSRET 31-0 target EIP address for SYSCALL SeeAlso: #R045 ----------SC0000081-------------------------- MSR C0000081h - AMD K6 - WRITE-HANDLING CONTROL REGISTER Size: 9 bits SeeAlso: MSR C0000080h,MSR C0000081h Bitfields for AMD K6 Write-Handling Control Register: Bit(s) Description (Table R047) 63-9 reserved 8 write cacheability detection enabled 7-1 write allocate enable limit (in 4M units) 0 write allocate enabled for 15-16M region --------!---CREDITS-------------------------- Christian Ludloff's 80x86.CPU Alex V. Potemkin's Opcodes List (OPCODES.LST) Intel Pentium Pro Family User's Guide, Volume 3, Appendix C --------!---Admin---------------------------- Highest Table Number = R047 --------!---FILELIST------------------------- Please redistribute all of the files comprising the interrupt list (listed at the beginning of the list and in INTERRUP.1ST) unmodified as a group, in a quartet of archives named INTER55A through INTER55D (preferably the original authenticated PKZIP archives), and the utility and hypertext conversion programs in three additional archives called INTER55E.ZIP to INTER55G.ZIP. Copyright (c) 1989,1990,1991,1992,1993,1994,1995,1996,1997 Ralf Brown --------!---CONTACT_INFO--------------------- Internet: ralf@pobox.com (currently forwards to ralf@telerama.lm.com) FIDO: Ralf Brown 1:129/26.1 or post a message to me in the DR_DEBUG echo (I probably won't see it unless you address it to me) CIS: >INTERNET:ralf@pobox.com