641 lines
19 KiB
PHP
641 lines
19 KiB
PHP
;---------------------------- Include File Header ---------------------------;
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; Module Name: hw.inc
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;
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; All the hardware specific driver file stuff. Mirrors some of 'hw.h'.
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;
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; Copyright (c) 1993-1995 Microsoft Corporation
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;----------------------------------------------------------------------------;
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; The following is used to define the MGA memory map.
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; MGA map
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SrcWin equ 00000h
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IntReg equ 01c00h
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DstWin equ 02000h
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ExtDev equ 03c00h
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; Internal registers
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DwgReg equ 00000h
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StartDwgReg equ 00100h
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HstReg equ 00200h
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VgaReg equ 00300h
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; External devices
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RamDac equ 00000h
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Dubic equ 00080h
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Viwic equ 00100h
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ClkGen equ 00180h
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ExpDev equ 00200h
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; TITAN registers
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DWGCTL equ 00000h
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MACCESS equ 00004h
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MCTLWTST equ 00008h
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DST0 equ 00010h
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DST1 equ 00014h
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ZMSK equ 00018h
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PLNWT equ 0001Ch
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BCOL equ 00020h
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FCOL equ 00024h
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SRCBLT equ 0002Ch
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SRC0 equ 00030h
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SRC1 equ 00034h
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SRC2 equ 00038h
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SRC3 equ 0003Ch
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XYSTRT equ 00040h
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XYEND equ 00044h
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SHIFT equ 00050h
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SGN equ 00058h
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LEN equ 0005Ch
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AR0 equ 00060h
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AR1 equ 00064h
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AR2 equ 00068h
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AR3 equ 0006Ch
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AR4 equ 00070h
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AR5 equ 00074h
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AR6 equ 00078h
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PITCH equ 0008Ch
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YDST equ 00090h
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YDSTORG equ 00094h
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CYTOP equ 00098h
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CYBOT equ 0009Ch
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CXLEFT equ 000A0h
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CXRIGHT equ 000A4h
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FXLEFT equ 000A8h
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FXRIGHT equ 000ACh
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XDST equ 000B0h
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ALU_DR0 equ 000C0h
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ALU_DR1 equ 000C4h
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ALU_DR2 equ 000C8h
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ALU_DR3 equ 000CCh
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ALU_DR4 equ 000D0h
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ALU_DR5 equ 000D4h
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ALU_DR6 equ 000D8h
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ALU_DR7 equ 000DCh
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ALU_DR8 equ 000E0h
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ALU_DR9 equ 000E4h
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ALU_DR10 equ 000E8h
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ALU_DR11 equ 000ECh
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ALU_DR12 equ 000F0h
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ALU_DR13 equ 000F4h
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ALU_DR14 equ 000F8h
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ALU_DR15 equ 000FCh
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; Host registers
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SRCPAGE equ 00000h
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DSTPAGE equ 00004h
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BYTACCDATA equ 00008h
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ADRGEN equ 0000Ch
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FIFOSTATUS equ 00010h
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STATUS equ 00014h
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ICLEAR equ 00018h
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IEN equ 0001Ch
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RST equ 00040h
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TESTBIT equ 00044h
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REV equ 00048h
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CONFIG_REG equ 00050h
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OPMODE equ 00054h
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CRTC_CTRL equ 0005Ch
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VCOUNT equ 00060h
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; Bt485
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BT485_PAL_OR_CURS_RAM_WRITE equ 00000h
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BT485_COLOR_PAL_DATA equ 00004h
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BT485_PIXEL_MASK equ 00008h
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BT485_PAL_OR_CURS_RAM_READ equ 0000Ch
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BT485_OVS_OR_CURS_COLOR_WRITE equ 00010h
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BT485_OVS_OR_CURS_COLOR_DATA equ 00014h
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BT485_COMMAND_0 equ 00018h
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BT485_OVS_OR_CURS_COLOR_READ equ 0001Ch
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BT485_COMMAND_1 equ 00020h
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BT485_COMMAND_2 equ 00024h
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BT485_COMMAND_3_OR_STATUS equ 00028h
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BT485_CURS_RAM_ARRAY equ 0002Ch
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BT485_CURS_X_LOW equ 00030h
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BT485_CURS_X_HIGH equ 00034h
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BT485_CURS_Y_LOW equ 00038h
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BT485_CURS_Y_HIGH equ 0003Ch
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; Bt482
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BT482_PAL_OR_CURS_RAM_WRITE equ 00000h
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BT482_COLOR_PAL_DATA equ 00004h
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BT482_PIXEL_MASK equ 00008h
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BT482_PAL_OR_CURS_RAM_READ equ 0000Ch
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BT482_OVS_OR_CURS_COLOR_WRITE equ 00010h
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BT482_OVS_OR_CURS_COLOR_DATA equ 00014h
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BT482_COMMAND_A equ 00018h
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BT482_OVS_OR_CURS_COLOR_READ equ 0001Ch
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; ViewPoint
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VPOINT_PAL_ADDR_WRITE equ 00000h
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VPOINT_PAL_COLOR equ 00004h
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VPOINT_PIX_READ_MASK equ 00008h
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VPOINT_PAL_ADDR_READ equ 0000ch
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VPOINT_RESERVED_4 equ 00010h
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VPOINT_RESERVED_5 equ 00014h
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VPOINT_INDEX equ 00018h
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VPOINT_DATA equ 0001ch
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; Dubic
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DUB_SEL equ 00080h
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NDX_PTR equ 00081h
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DUB_DATA equ 00082h
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LASER equ 00083h
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MOUSE0 equ 00084h
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MOUSE1 equ 00085h
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MOUSE2 equ 00086h
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MOUSE3 equ 00087h
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; Index within NDX_PTR to access the following registers through DUB_DATA
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DUB_CTL equ 000h
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KEY_COL equ 001h
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KEY_MSK equ 002h
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DBX_MIN equ 003h
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DBX_MAX equ 004h
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DBY_MIN equ 005h
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DBY_MAX equ 006h
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OVS_COL equ 007h
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CUR_X equ 008h
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CUR_Y equ 009h
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DUB_CTL2 equ 00Ah
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DUB_UnDef equ 00Bh
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CUR_COL0 equ 00Ch
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CUR_COL1 equ 00Dh
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CRC_CTL equ 00Eh
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CRC_DAT equ 00Fh
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; **************************************************************************
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; Titan registers: fields definitions
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; DWGCTRL - Drawing Control Register
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opcode_LINE_OPEN equ 000000000h
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opcode_AUTOLINE_OPEN equ 000000001h
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opcode_LINE_CLOSE equ 000000002h
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opcode_AUTOLINE_CLOSE equ 000000003h
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opcode_AUTO equ 000000001h
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opcode_TRAP equ 000000004h
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opcode_RESERVED_1 equ 000000005h
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opcode_RESERVED_2 equ 000000006h
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opcode_RESERVED_3 equ 000000007h
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opcode_BITBLT equ 000000008h
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opcode_ILOAD equ 000000009h
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opcode_IDUMP equ 00000000ah
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opcode_RESERVED_4 equ 00000000bh
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opcode_RESERVED_5 equ 00000000ch
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opcode_RESERVED_6 equ 00000000dh
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opcode_RESERVED_7 equ 00000000eh
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opcode_RESERVED_8 equ 00000000fh
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atype_RPL equ 000000000h
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atype_RSTR equ 000000010h
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atype_ANTI equ 000000020h
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atype_ZI equ 000000030h
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blockm_ON equ 000000040h
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blockm_OFF equ 000000000h
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linear_XY_BITBLT equ 000000000h
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linear_LINEAR_BITBLT equ 000000080h
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bop_BLACK equ 000000000h ; 0 0
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bop_BLACKNESS equ 000000000h ; 0 0
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bop_NOTMERGEPEN equ 000010000h ; DPon ~(D | S)
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bop_MASKNOTPEN equ 000020000h ; DPna D & ~S
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bop_NOTCOPYPEN equ 000030000h ; Pn ~S
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bop_MASKPENNOT equ 000040000h ; PDna (~D) & S
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bop_NOT equ 000050000h ; Dn ~D
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bop_XORPEN equ 000060000h ; DPx D ^ S
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bop_NOTMASKPEN equ 000070000h ; DPan ~(D & S)
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bop_MASKPEN equ 000080000h ; DPa D & S
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bop_NOTXORPEN equ 000090000h ; DPxn ~(D ^ S)
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bop_NOP equ 0000a0000h ; D D
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bop_MERGENOTPEN equ 0000b0000h ; DPno D | ~S
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bop_COPYPEN equ 0000c0000h ; P S
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bop_SRCCOPY equ 0000c0000h ; P S
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bop_MERGEPENNOT equ 0000d0000h ; PDno (~D)| S
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bop_MERGEPEN equ 0000e0000h ; DPo D | S
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bop_WHITE equ 0000f0000h ; 1 1
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bop_WHITENESS equ 0000f0000h ; 1 1
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trans_0 equ 000000000h
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trans_1 equ 000100000h
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trans_2 equ 000200000h
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trans_3 equ 000300000h
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trans_4 equ 000400000h
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trans_5 equ 000500000h
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trans_6 equ 000600000h
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trans_7 equ 000700000h
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trans_8 equ 000800000h
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trans_9 equ 000900000h
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trans_10 equ 000a00000h
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trans_11 equ 000b00000h
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trans_12 equ 000c00000h
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trans_13 equ 000d00000h
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trans_14 equ 000e00000h
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trans_15 equ 000f00000h
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alphadit_FOREGROUND equ 000000000h
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alphadit_RED equ 001000000h
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bltmod_BMONO equ 000000000h
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bltmod_BPLAN equ 002000000h
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bltmod_BFCOL equ 004000000h
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bltmod_BUCOL equ 006000000h
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zdrwen_NO_DEPTH equ 000000000h
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zdrwen_DEPTH equ 002000000h
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zlte_LESS_THEN equ 000000000h
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zlte_LESS_THEN_OR_EQUAL equ 004000000h
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afor_DATA_ALU equ 000000000h
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afor_FORE_COL equ 008000000h
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hbgr_SRC_RGB equ 000000000h
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hbgr_SRC_BGR equ 008000000h
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hbgr_SRC_EG3 equ 000000000h
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hbgr_SRC_WINDOWS equ 008000000h
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abac_OLD_DATA equ 000000000h
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abac_BG_COLOR equ 010000000h
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hcprs_SRC_32_BPP equ 000000000h
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hcprs_SRC_24_BPP equ 010000000h
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pattern_OFF equ 000000000h
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pattern_ON equ 020000000h
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transc_BIT equ 0h ; bit #30
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transc_BG_OPAQUE equ 000000000h
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transc_BG_TRANSP equ 040000000h
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; MACCESS - Memory Access Register
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pwidth_PW8 equ 000000000h
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pwidth_PW16 equ 000000001h
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pwidth_PW32 equ 000000002h
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pwidth_RESERVED equ 000000003h
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fbc_SBUF equ 000000000h
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fbc_RESERVED equ 000000004h
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fbc_DBUFA equ 000000008h
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fbc_DBUFB equ 00000000ch
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; MCTLWTST - Memory Control Wait State Register
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; DST0, DST1 - Destination in Register
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; ZMASK - Z Mask Control Register
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; PLNWT - Plane Write Mask
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plnwt_MASK_8BPP equ 0ffffffffh
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plnwt_MASK_16BPP equ 0ffffffffh
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plnwt_MASK_24BPP equ 000ffffffh
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plnwt_ALL equ 0ffffffffh
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plnwt_FREE equ 0ff000000h
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plnwt_RED equ 000ff0000h
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plnwt_GREEN equ 00000ff00h
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plnwt_BLUE equ 0000000ffh
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; BCOL - Background Color
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; FCOL - ForeGround Color
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; SRCBLT - Source Register for Blit
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; SRC0, SRC1, SRC2, SRC3 - Source Register
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; XYSTART - X Y Start Address
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; XYEND - X Y End Address
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; SHIFT - Funnel Shifter Control Register
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funoff_MASK equ 0ffc0ffffh
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funoff_RED_TO_FREE equ 000380000h ; -8
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funoff_GREEN_TO_FREE equ 000300000h ; -16
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funoff_BLUE_TO_FREE equ 000280000h ; -24
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funoff_FREE_TO_RED equ 000080000h ; 8
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funoff_FREE_TO_GREEN equ 000100000h ; 16
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funoff_FREE_TO_BLUE equ 000180000h ; 24
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funoff_X_TO_FREE_STEP equ 000080000h
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funoff_FREE_TO_X_STEP equ 000080000h
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; SGN - Sign Register
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sdydxl_MAJOR_Y equ 000000000h
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sdydxl_MAJOR_X equ 000000001h
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scanleft_LEFT equ 000000001h
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scanleft_RIGHT equ 000000000h
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sdxl_ADD equ 000000000h
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sdxl_SUB equ 000000002h
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sdy_ADD equ 000000000h
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sdy_SUB equ 000000004h
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sdxr_INC equ 000000000h
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sdxr_DEC equ 000000020h
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scanleft_LEFT_TO_RIGHT equ 000000000h
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scanleft_RIGHT_TO_LEFT equ 000000001h
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sdy_TOP_TO_BOTTOM equ 000000000h
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sdy_BOTTOM_TO_TOP equ 000000004h
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DRAWING_DIR_TBLR equ y_TOP_TO_BOTTOM+scanleft_RIGHT ; 0x00
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DRAWING_DIR_TBRL equ y_TOP_TO_BOTTOM+scanleft_LEFT ; 0x01
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DRAWING_DIR_BTLR equ y_BOTTOM_TO_TOP+scanleft_RIGHT ; 0x04
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DRAWING_DIR_BTRL equ y_BOTTOM_TO_TOP+scanleft_LEFT ; 0x05
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; LEN - length register
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; AR0
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ARX_BIT_MASK equ 00001ffffh
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; AR1
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; AR2
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; AR3
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; AR4
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; AR5
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; AR6
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; PITCH - Memory Pitch
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iy_512 equ 000000200h
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iy_640 equ 000000280h
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iy_768 equ 000000300h
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iy_800 equ 000000320h
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iy_1024 equ 000000400h
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iy_1152 equ 000000480h
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iy_1280 equ 000000500h
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iy_1536 equ 000000600h
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iy_1600 equ 000000640h
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ylin_LINEARIZE equ 000000000h
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ylin_LINEARIZE_NOT equ 000008000h
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iy_MASK equ 000001fe0h
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; YDST - Y Address Register
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; YDSTORG - memory origin register
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; YTOP - Clipper Y Top Boundary
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; YBOT - Clipper Y Bottom Boundary
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; CXLEFT - Clipper X Minimum Boundary
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; CXRIGHT - Clipper X Maximum Boundary
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; FXLEFT - X Address Register (Left)
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; FXRIGHT - X Address Register (Right)
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; XDST - X Destination Address Register
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; DR0
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; DR1
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; DR2
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; DR3
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; DR4
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; DR5
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; DR6
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; DR7
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; DR8
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; DR9
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; DR10
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; DR11
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; DR12
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; DR13
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; DR14
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; DR15
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; **************************************************************************
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; Host registers: fields definitions
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; SRCPAGE - Source Page Register
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; DSTPAGE - Destination Page Register
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; BYTEACCDATA - Byte Accumulator Data
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; ADRGEN - Address Generator Register
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; FIFOSTATUS - Bus FIFO Status Register
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fifocount_MASK equ 00000007fh
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bfull_MASK equ 000000100h
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bempty_MASK equ 000000200h
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byteaccaddr_MASK equ 0007f0000h
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addrgenstate_MASK equ 03f000000h
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; STATUS - Status Register
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bferrists_MASK equ 000000001h
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dmatcists_MASK equ 000000002h
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pickists_MASK equ 000000004h
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vsyncsts_MASK equ 000000008h
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byteflag_MASK equ 000000f00h
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dwgengsts_MASK equ 000010000h
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; ICLEAR - Interrupt Clear Register
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bferriclr_OFF equ 000000000h
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bferriclr_ON equ 000000001h
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dmactciclr_OFF equ 000000000h
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dmactciclr_ON equ 000000002h
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pickiclr_OFF equ 000000000h
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pickiclr_ON equ 000000004h
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; IEN - Interrupt Enable Register
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bferrien_OFF equ 000000000h
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bferrien_ON equ 000000001h
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dmactien_OFF equ 000000000h
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dmactien_ON equ 000000002h
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pickien_OFF equ 000000000h
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pickien_ON equ 000000004h
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vsyncien_OFF equ 000000000h
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vsyncien_ON equ 000000008h
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; RST - Reset Register
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softreset equ 000000001h
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; TEST - Test Register
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vgatest equ 000000001h
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robitwren equ 000000100h
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; REV - Revision Register
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; CONFIG_REG - Configuration Register
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; OPMODE - Operating Mode Register
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OPMODE_OTHER_INFO equ 0fffffff0h
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pseudodma_OFF equ 000000000h
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pseudodma_ON equ 000000001h
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dmaact_OFF equ 000000000h
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dmaact_ON equ 000000002h
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dmamod_GENERAL_PURPOSE equ 000000000h
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dmamod_BLIT_WRITE equ 000000004h
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dmamod_VECTOR_WRITE equ 000000008h
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dmamod_BLIT_READ equ 00000000ch
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; CRTC_CTRL - CRTC Control
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; VCOUNT - VCOUNT Register
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; COLOR PATTERN
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PATTERN_PITCH equ 0
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; DMA
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DMAWINSIZE equ 1024 / 4 ; 7k in DWORDS
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; FIFO
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FIFOSIZE equ 0
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INTEL_PAGESIZE equ 1024 ; 4k bytes per page
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INTEL_PAGESIZE_DW equ 1024/4 ; 1k dwords per page
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; Accelerator flags
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NO_CACHE equ 0
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SIGN_CACHE equ 1 ; 1 is also the nb of registers affected
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ARX_CACHE equ 2
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PATTERN_CACHE equ 4 ; 4 is also the nb of registers affected
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; MGA Rop definitions
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MGA_BLACKNESS equ 00000h ; 0 0
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MGA_NOTMERGEPEN equ 00001h ; DPon ~(D | S)
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MGA_MASKNOTPEN equ 00002h ; DPna D & ~S
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MGA_NOTCOPYPEN equ 00003h ; Pn ~S
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MGA_MASKPENNOT equ 00004h ; PDna (~D) & S
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MGA_NOT equ 00005h ; Dn ~D
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MGA_XORPEN equ 00006h ; DPx D ^ S
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MGA_NOTMASKPEN equ 00007h ; DPan ~(D & S)
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MGA_MASKPEN equ 00008h ; DPa D & S
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MGA_NOTXORPEN equ 00009h ; DPxn ~(D ^ S)
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MGA_NOP equ 0000ah ; D D
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MGA_MERGENOTPEN equ 0000bh ; DPno D | ~S
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MGA_SRCCOPY equ 0000ch ; P S
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MGA_MERGEPENNOT equ 0000dh ; PDno (~D)| S
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MGA_MERGEPEN equ 0000eh ; DPo D | S
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MGA_WHITENESS equ 0000fh ; 1 1
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; Special MCTLWTST value for IDUMPs
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IDUMP_MCTLWTST equ 0c4001000h
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; **************************************************************************
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; Explicit register offsets.
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DMAWND equ SrcWin
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SRCWND equ SrcWin
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DSTWND equ DstWin
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DWG_DWGCTL equ IntReg+DwgReg+DWGCTL
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DWG_MACCESS equ IntReg+DwgReg+MACCESS
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DWG_MCTLWTST equ IntReg+DwgReg+MCTLWTST
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DWG_DST0 equ IntReg+DwgReg+DST0
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DWG_DST1 equ IntReg+DwgReg+DST1
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DWG_ZMSK equ IntReg+DwgReg+ZMSK
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DWG_PLNWT equ IntReg+DwgReg+PLNWT
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DWG_BCOL equ IntReg+DwgReg+BCOL
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DWG_FCOL equ IntReg+DwgReg+FCOL
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DWG_SRCBLT equ IntReg+DwgReg+SRCBLT
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DWG_SRC0 equ IntReg+DwgReg+SRC0
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DWG_SRC1 equ IntReg+DwgReg+SRC1
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DWG_SRC2 equ IntReg+DwgReg+SRC2
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DWG_SRC3 equ IntReg+DwgReg+SRC3
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DWG_XYSTRT equ IntReg+DwgReg+XYSTRT
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DWG_XYEND equ IntReg+DwgReg+XYEND
|
|
DWG_SHIFT equ IntReg+DwgReg+SHIFT
|
|
DWG_SGN equ IntReg+DwgReg+SGN
|
|
DWG_LEN equ IntReg+DwgReg+LEN
|
|
DWG_AR0 equ IntReg+DwgReg+AR0
|
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DWG_AR1 equ IntReg+DwgReg+AR1
|
|
DWG_AR2 equ IntReg+DwgReg+AR2
|
|
DWG_AR3 equ IntReg+DwgReg+AR3
|
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DWG_AR4 equ IntReg+DwgReg+AR4
|
|
DWG_AR5 equ IntReg+DwgReg+AR5
|
|
DWG_AR6 equ IntReg+DwgReg+AR6
|
|
DWG_PITCH equ IntReg+DwgReg+PITCH
|
|
DWG_YDST equ IntReg+DwgReg+YDST
|
|
DWG_YDSTORG equ IntReg+DwgReg+YDSTORG
|
|
DWG_CYTOP equ IntReg+DwgReg+CYTOP
|
|
DWG_CYBOT equ IntReg+DwgReg+CYBOT
|
|
DWG_CXLEFT equ IntReg+DwgReg+CXLEFT
|
|
DWG_CXRIGHT equ IntReg+DwgReg+CXRIGHT
|
|
DWG_FXLEFT equ IntReg+DwgReg+FXLEFT
|
|
DWG_FXRIGHT equ IntReg+DwgReg+FXRIGHT
|
|
DWG_XDST equ IntReg+DwgReg+XDST
|
|
DWG_DR0 equ IntReg+DwgReg+DR0
|
|
DWG_DR1 equ IntReg+DwgReg+DR1
|
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DWG_DR2 equ IntReg+DwgReg+DR2
|
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DWG_DR3 equ IntReg+DwgReg+DR3
|
|
DWG_DR4 equ IntReg+DwgReg+DR4
|
|
DWG_DR5 equ IntReg+DwgReg+DR5
|
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DWG_DR6 equ IntReg+DwgReg+DR6
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DWG_DR7 equ IntReg+DwgReg+DR7
|
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DWG_DR8 equ IntReg+DwgReg+DR8
|
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DWG_DR9 equ IntReg+DwgReg+DR9
|
|
DWG_DR10 equ IntReg+DwgReg+DR10
|
|
DWG_DR11 equ IntReg+DwgReg+DR11
|
|
DWG_DR12 equ IntReg+DwgReg+DR12
|
|
DWG_DR13 equ IntReg+DwgReg+DR13
|
|
DWG_DR14 equ IntReg+DwgReg+DR14
|
|
DWG_DR15 equ IntReg+DwgReg+DR15
|
|
|
|
HST_SRCPAGE equ IntReg+HstReg+SRCPAGE
|
|
HST_DSTPAGE equ IntReg+HstReg+DSTPAGE
|
|
HST_BYTACCDATA equ IntReg+HstReg+BYTACCDATA
|
|
HST_ADRGEN equ IntReg+HstReg+ADRGEN
|
|
HST_FIFOSTATUS equ IntReg+HstReg+FIFOSTATUS
|
|
HST_STATUS equ IntReg+HstReg+STATUS
|
|
HST_ICLEAR equ IntReg+HstReg+ICLEAR
|
|
HST_IEN equ IntReg+HstReg+IEN
|
|
HST_RST equ IntReg+HstReg+RST
|
|
HST_TEST equ IntReg+HstReg+TEST
|
|
HST_REV equ IntReg+HstReg+REV
|
|
HST_CONFIG_REG equ IntReg+HstReg+CONFIG_REG
|
|
HST_OPMODE equ IntReg+HstReg+OPMODE
|
|
HST_CRTC_CTRL equ IntReg+HstReg+CRTC_CTRL
|
|
HST_VCOUNT equ IntReg+HstReg+VCOUNT
|
|
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