223 lines
6.9 KiB
C
223 lines
6.9 KiB
C
/**************************************************************************
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*
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* $RCSfile:$
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* $Source:$
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* $Author:$
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* $Date:$
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* $Revision:$
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*
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*
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* Program the AUDIO DAC
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*
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* This routine is only for the Burr Brown PCM1721
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*
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* Copyright (C) 1993, 1997 AuraVision Corporation. All rights reserved.
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*
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* AuraVision Corporation makes no warranty of any kind, express or
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* implied, with regard to this software. In no event shall AuraVision
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* Corporation be liable for incidental or consequential damages in
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* connection with or arising from the furnishing, performance, or use of
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* this software.
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*
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***************************************************************************/
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#ifdef VTOOLSD
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#include <vtoolsc.h>
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#include "monovxd.h"
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#else
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#include "Headers.h"
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#pragma hdrstop
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#endif
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#include "audiodac.h"
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#include "fpga.h"
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#include "boardio.h"
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// Register Masks
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#define AUDIO_DAC_REG_0 0x0000
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#define AUDIO_DAC_REG_1 0x0200
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#define AUDIO_DAC_REG_2 0x0400
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#define AUDIO_DAC_REG_3 0x0600
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// Register 0 Defines
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#define AUDIO_DAC_R0_VOLUME 0x00FF // Left Channel Volume Mask
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#define AUDIO_DAC_R0_LDL 0x0100 // Simultanous Level Control
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// Register 1 Defines
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#define AUDIO_DAC_R1_VOLUME 0x00FF // Right Channel Volume Mask
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#define AUDIO_DAC_R1_LDR 0x0100 // Simultanous Level Control
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// Register 2 Defines
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#define AUDIO_DAC_R2_MUTE 0x0001 // Output Muting
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#define AUDIO_DAC_R2_DEM 0x0002 // De-Emphasis
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#define AUDIO_DAC_R2_OPE 0x0004 // Operation Control
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#define AUDIO_DAC_R2_16BIT 0x0000 // 16 Bit Input Resolution
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#define AUDIO_DAC_R2_20BIT 0x0008 // 20 Bit Input Resolution
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#define AUDIO_DAC_R2_24BIT 0x0010 // 24 Bit Input Resolution
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#define AUDIO_DAC_R2_BIT_MASK 0x0018 // Input Resolution - Mask
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#define AUDIO_DAC_R2_O_MUTE 0x0000 // Output Format - Mute
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#define AUDIO_DAC_R2_O_STEREO 0x0120 // Output Format - Stereo
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#define AUDIO_DAC_R2_O_MONO 0x01E0 // Output Format - Mono
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// Register 3 Defines
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#define AUDIO_DAC_R3_I2S 0x0001 // Philips I2S Format
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#define AUDIO_DAC_R3_LRP 0x0002 // Left Channel -> LRCIN "Low"
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#define AUDIO_DAC_R3_ATC 0x0004 // Attenuator Control
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#define AUDIO_DAC_R3_SYS_384 0x0000 // System Clock = 384 fS
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#define AUDIO_DAC_R3_SYS_256 0x0008 // System Clock = 256 fS
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#define AUDIO_DAC_R3_M_NORMAL 0x0000 // Multiple Control - Normal
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#define AUDIO_DAC_R3_M_DOUBLE 0x0010 // Multiple Control - Double
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#define AUDIO_DAC_R3_M_HALF 0x0020 // Multiple Control - Half
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#define AUDIO_DAC_R3_M_MASK 0x0030 // Multiple Control - Mask
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#define AUDIO_DAC_R3_SF_44 0x0000 // Sampling Frequency - 44.1k Group
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#define AUDIO_DAC_R3_SF_48 0x0040 // Sampling Frequency - 48k Group
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#define AUDIO_DAC_R3_SF_32 0x0080 // Sampling Frequency - 32k Group
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#define AUDIO_DAC_R3_SF_MASK 0x00C0 // Sampling Frequency - Mask
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#define AUDIO_DAC_R3_IZD 0x0100 // Zero Detect Circuit
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void Write_Audio_Register( WORD Index, WORD Data )
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{
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BYTE value;
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int i; // signed integer
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Index <<= 9;
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Data = Data | Index;
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// Set the AUDIO DAC strobe high
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FPGA_Set( AUDIO_STROBE );
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// Clean up the I2C register
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IHW_SetRegister(0x34,0);
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// Shift out the MSB first
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for ( i = 15; i >= 0 ; i-- )
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{
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value = ( ( Data >> i ) & 0x1 ) ? 0x04 : 0x0;
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IHW_SetRegister(0x34, value);
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IHW_SetRegister(0x34, (BYTE)(value | 0x01)); // Rising edge
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IHW_SetRegister(0x34, value);
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}
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FPGA_Clear( AUDIO_STROBE );
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FPGA_Set( AUDIO_STROBE );
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}
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static WORD wAUDAC_R0;
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static WORD wAUDAC_R1;
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static WORD wAUDAC_R2;
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static WORD wAUDAC_R3;
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//
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// Audio DAC Initialization
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//
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void ADAC_Init( DWORD dwBaseAddress )
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{
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// Setup Register 0
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wAUDAC_R0 = AUDIO_DAC_REG_0 | // Select Register 0
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// AUDIO_DAC_R0_LDL | // Load Flag
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AUDIO_DAC_R0_VOLUME; // Set Max Left Channel Level
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// Setup Register 1
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wAUDAC_R1 = AUDIO_DAC_REG_1 | // Select Register 1
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// AUDIO_DAC_R1_LDR | // Load Flag
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AUDIO_DAC_R1_VOLUME; // Set Max Right Channel Level
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// Setup Register 2
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wAUDAC_R2 = AUDIO_DAC_REG_2 | // Select Register 2
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AUDIO_DAC_R2_16BIT | // 16 Bit Operation
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AUDIO_DAC_R2_O_STEREO; // Stereo Format
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// Setup Register 3
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wAUDAC_R3 = AUDIO_DAC_REG_3 | // Select Register 3
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// AUDIO_DAC_R3_I2S |
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AUDIO_DAC_R3_SYS_384 | // 384*fS Sampling
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AUDIO_DAC_R3_M_NORMAL | // Normal Multiple
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AUDIO_DAC_R3_SF_48; // 48 kHz Group
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// Write attenuation values for left and right channels
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Write_Audio_Register( 0, wAUDAC_R0 );
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Write_Audio_Register( 1, wAUDAC_R1 );
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// Lock attenuation values for left and right channels
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Write_Audio_Register( 0, (WORD)(wAUDAC_R0|AUDIO_DAC_R0_LDL) );
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Write_Audio_Register( 1, (WORD)(wAUDAC_R1|AUDIO_DAC_R1_LDR) );
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Write_Audio_Register( 2, wAUDAC_R2 );
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Write_Audio_Register( 3, wAUDAC_R3 );
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}
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//
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// Set Sampling Frequency and Bit Number
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//
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// Sampling Frequencies:
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// 44 -> 44.1 kHz
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// 48 -> 48 kHz
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// 96 -> 96 kHz
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//
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// Bit Number
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// 16
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// 20
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// 24
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//
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void ADAC_SetSamplingFrequency( ADAC_SAMPLING_FREQ SamplingFrequency )
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{
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wAUDAC_R3 &= ~AUDIO_DAC_R3_M_MASK; // Mask Multiple Control
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wAUDAC_R3 &= ~AUDIO_DAC_R3_SF_MASK; // Mask Sampling Frequency
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switch( SamplingFrequency )
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{
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case ADAC_SAMPLING_FREQ_44:
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wAUDAC_R3 |= (AUDIO_DAC_R3_M_NORMAL | AUDIO_DAC_R3_SF_44);
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break;
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case ADAC_SAMPLING_FREQ_48:
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wAUDAC_R3 |= (AUDIO_DAC_R3_M_NORMAL | AUDIO_DAC_R3_SF_48);
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break;
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case ADAC_SAMPLING_FREQ_96:
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wAUDAC_R3 |= (AUDIO_DAC_R3_M_DOUBLE | AUDIO_DAC_R3_SF_48);
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break;
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}
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// Send new values
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Write_Audio_Register( 3, wAUDAC_R3 );
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}
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void ADAC_SetInputResolution( ADAC_INPUT_RESOLUTION InputResolution )
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{
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// Mask out Bit Number and Set Value
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wAUDAC_R2 &= ~AUDIO_DAC_R2_BIT_MASK; // Mask Bit Number
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switch( InputResolution )
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{
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case ADAC_INPUT_RESOLUTION_16:
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wAUDAC_R2 |= AUDIO_DAC_R2_16BIT; // Set 16 Bit
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break;
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case ADAC_INPUT_RESOLUTION_20:
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wAUDAC_R2 |= AUDIO_DAC_R2_20BIT; // Set 20 Bit
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break;
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case ADAC_INPUT_RESOLUTION_24:
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wAUDAC_R2 |= AUDIO_DAC_R2_24BIT; // Set 24 Bit
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break;
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}
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// Send new values
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Write_Audio_Register( 2, wAUDAC_R2 );
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}
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//
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// Mutes Audio Output
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// Mute
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// TRUE -> Mute
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// FALSE -> Unmute
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//
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void ADAC_Mute( BOOL Mute )
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{
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wAUDAC_R2 &= ~AUDIO_DAC_R2_MUTE; // Mask Mute
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if ( Mute == TRUE )
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wAUDAC_R2 |= AUDIO_DAC_R2_MUTE; // Set Mute
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// Send new value
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Write_Audio_Register( 2, wAUDAC_R2 );
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}
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