161 lines
6.8 KiB
C
161 lines
6.8 KiB
C
//----------------------------------------------------------------------------
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// PCI9060.C
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//----------------------------------------------------------------------------
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// PCI bridge (PLX PCI9060) programming
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//----------------------------------------------------------------------------
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// Copyright SGS Thomson Microelectronics ! Version alpha ! Jan 1st, 1995
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Include files
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//----------------------------------------------------------------------------
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#include "stdefs.h"
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#include "debug.h"
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#include "error.h"
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#include "aal.h"
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//----------------------------------------------------------------------------
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// Private Constants
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//----------------------------------------------------------------------------
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//---- RESET address
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#define RESET 0x0800
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//---- RESET register bit
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#define RST9060 0x02
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//---- Misc
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#define PLX_VENDOR_ID 0x10b5 // not used at all
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#define PCI_9060_DEVICE_ID 0x9060 // not used at all
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//---- PCI configuration registers type bits
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#define PCI9060_VENDOR_ID 0x000 // 16
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#define PCI9060_DEVICE_ID 0x002 // 16
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#define PCI9060_COMMAND 0x004 // 16
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#define PCI9060_STATUS 0x006 // 16
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#define PCI9060_REV_ID 0x008 // 8
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#define PCI9060_CLASS_PI 0x009 // 8
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#define PCI9060_CLASS_SUB 0x00A // 8
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#define PCI9060_CLASS_BASE 0x00B // 8
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#define PCI9060_CACHE_SIZE 0x00C // 8
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#define PCI9060_LATENCY_TIMER 0x00D // 8
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#define PCI9060_HEADER_TYPE 0x00E // 8
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#define PCI9060_BIST 0x00F // 8
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#define PCI9060_RTR_BASE 0x010 // 32
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#define PCI9060_RTR_IO_BASE 0x014 // 32
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#define PCI9060_LOCAL_BASE 0x018 // 32
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#define PCI9060_EXP_BASE 0x030 // 32
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#define PCI9060_LAT_GNT_INTPIN_INTLINE 0x03C // 32
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//---- PLX registers
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#define PCI9060_LOCAL_RANGE 0x000 // 32
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#define PCI9060_LOCAL_REMAP 0x004 // 32
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#define PCI9060_EXP_RANGE 0x010 // 32
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#define PCI9060_EXP_REMAP 0x014 // 32
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#define PCI9060_REGIONS 0x018 // 32
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#define PCI9060_DM_MASK 0x01c // 32
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#define PCI9060_DM_LOCAL_BASE 0x020 // 32
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#define PCI9060_DM_IO_BASE 0x024 // 32
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#define PCI9060_DM_PCI_REMAP 0x028 // 32
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#define PCI9060_DM_IO_CONFIG 0x02C // 32
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#define PCI9060_MAILBOX 0x040 // 32
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#define PCI9060_LOCAL_DOORBELL 0x060 // 32
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#define PCI9060_PCI_DOORBELL 0x064 // 32
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#define PCI9060_INT_CONTROL_STATUS 0x068 // 32
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#define PCI9060_EEPROM_CONTROL_STATUS 0x06C // 32
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//---- Register bits
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#define EEPROM_CK 0x01000000UL // EEPROM Clock
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#define EEPROM_CS 0x02000000UL // EEPROM Chip Select
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#define EEPROM_WR 0x04000000UL // EEPROM input
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#define EEPROM_RD 0x08000000UL // EEPROM output
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//----------------------------------------------------------------------------
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// Private Types
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Private GLOBAL Variables (static)
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Functions (statics one are private)
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Test of PCI9060 registers
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//----------------------------------------------------------------------------
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BOOL PCI9060TestRegisters(VOID)
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{
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//---- Test PCI9060_MAILBOX
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PCI9060Out32(PCI9060_MAILBOX + 0, 0xAA5555AAUL);
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PCI9060Out32(PCI9060_MAILBOX + 4, 0x55AAAA55UL);
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if (PCI9060In32(PCI9060_MAILBOX + 0) != 0xAA5555AAUL)
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goto Error;
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if (PCI9060In32(PCI9060_MAILBOX + 4) != 0x55AAAA55UL)
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goto Error;
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return TRUE;
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Error :
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DebugPrint((DebugLevelError, "PCI9060 register test failed !"));
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SetErrorCode(ERR_PCI9060_REG_TEST_FAILED);
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return FALSE;
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}
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//----------------------------------------------------------------------------
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//
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//----------------------------------------------------------------------------
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VOID PCI9060EEPROMWriteCMD(BOOL Clock, BOOL ChipSelect, BOOL Write)
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{
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if (ChipSelect) {
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if (Clock && Write)
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PCI9060Out32(PCI9060_EEPROM_CONTROL_STATUS, EEPROM_CS | EEPROM_CK | EEPROM_WR);
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else if (Clock && !Write)
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PCI9060Out32(PCI9060_EEPROM_CONTROL_STATUS, EEPROM_CS | EEPROM_CK);
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else if (!Clock && Write)
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PCI9060Out32(PCI9060_EEPROM_CONTROL_STATUS, EEPROM_CS | EEPROM_WR);
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else if (!Clock && !Write)
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PCI9060Out32(PCI9060_EEPROM_CONTROL_STATUS, EEPROM_CS);
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else
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DebugPrint((DebugLevelFatal, "Case not possible !"));
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}
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else {
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if (Clock && Write)
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PCI9060Out32(PCI9060_EEPROM_CONTROL_STATUS, EEPROM_CK | EEPROM_WR);
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else if (Clock && !Write)
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PCI9060Out32(PCI9060_EEPROM_CONTROL_STATUS, EEPROM_CK);
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else if (!Clock && Write)
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PCI9060Out32(PCI9060_EEPROM_CONTROL_STATUS, EEPROM_WR);
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else if (!Clock && !Write)
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PCI9060Out32(PCI9060_EEPROM_CONTROL_STATUS, 0);
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else
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DebugPrint((DebugLevelFatal, "Case not possible !"));
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}
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}
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//----------------------------------------------------------------------------
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//
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//----------------------------------------------------------------------------
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BOOL PCI9060EEPROMRead(VOID)
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{
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return (PCI9060In8(PCI9060_EEPROM_CONTROL_STATUS + 2) & EEPROM_RD) != 0;
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}
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//----------------------------------------------------------------------------
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// Enable LINTI# to generate INTA#
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//----------------------------------------------------------------------------
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VOID PCI9060EnableIRQ(VOID)
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{
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PCI9060Out32(PCI9060_INT_CONTROL_STATUS, PCI9060In32(PCI9060_INT_CONTROL_STATUS) | 0x00000800UL);
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}
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//----------------------------------------------------------------------------
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// Disable LINTI# to generate INTA#
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//----------------------------------------------------------------------------
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VOID PCI9060DisableIRQ(VOID)
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{
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PCI9060Out32(PCI9060_INT_CONTROL_STATUS, PCI9060In32(PCI9060_INT_CONTROL_STATUS) & ~0x00000800UL);
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}
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//------------------------------- End of File --------------------------------
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