153 lines
4.2 KiB
C
153 lines
4.2 KiB
C
/**********************************************************
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* Copyright Cirrus Logic, 1997. All rights reserved.
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***********************************************************
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*
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* 5465BW.H - Bandwidth function header for CL-GD5465
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*
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***********************************************************
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*
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* Author: Rick Tillery
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* Date: 03/20/97
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*
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* Revision History:
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* -----------------
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* WHO WHEN WHAT/WHY/HOW
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* --- ---- ------------
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*
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***********************************************************/
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// If WinNT 3.5 skip all the source code
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#if defined WINNT_VER35 // WINNT_VER35
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#else
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#ifndef _5465BW_H
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#define _5465BW_H
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#ifndef WINNT_VER40
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#include <Windows.h>
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#endif
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#ifdef DEBUGSTRINGS
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#ifndef ODS
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extern void __cdecl Msg( LPSTR szFormat, ... );
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#define ODS Msg
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#endif // ODS
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#else
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#ifndef ODS
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#define ODS (void)
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#endif // ODS
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#endif // DEBUGSTRINGS
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#ifdef _DEBUG
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#define BREAK1 _asm int 01h
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#define BREAK3 _asm int 03h
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#else
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#define BREAK1
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#define BREAK3
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#endif // _DEBUG
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#include "BW.h"
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#include <stdlib.h>
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//
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// CL-GD5465 specifications
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//
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#define FIFOWIDTH 64 // Bits
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#define BLTFIFOSIZE 32 // QWORDS
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#define CAPFIFOSIZE 16 // QWORDS
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#define GFXFIFOSIZE 64 // QWORDS
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#define VIDFIFOSIZE 32 // QWORDS
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#define NORM_RANDOM 14 // MCLKs for random access
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#ifndef OLDONE
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#define CONC_RANDOM 8 // MCLKs for concurrent random access
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#define CONC_HIT_LATENCY (8 - 2) // MCLKs for concurrent hit minus
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#else
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#define CONC_RANDOM 10 // MCLKs for concurrent random access
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#define CONC_HIT_LATENCY 8 // MCLKs for concurrent hit minus
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#endif
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#define NORM_HIT_LATENCY (4 - 2) // MCLKs for hit minus MCLK/VCLK sync
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// MCLK/VCLK sync
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#define RIF_SAVINGS 4 // MCLKs savings for sequential randoms
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#define SYNCDELAY 3 // MCLKs for synchronization delay to
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// account for VCLK/MCLK sync, state
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// machine and RIF delays
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#define DISP_LATENCY 6ul // Max delay through display arbitraion
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// pipeline.
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#define ONEVIDLEVELFILL 2 // MCLKs to fill one video FIFO level
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#define ONELEVEL 1
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#define ARBSYNC 5 // Arbitration sync (pipelining)
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#define CURSORFILL 2
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#define BLTFILL (BLTFIFOSIZE / 2) // MCLKs to burst fill BLT FIFO
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#define CAPFILL (CAPFIFOSIZE / 2) // MCLKs to burst fill capture FIFO
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#define VIDFILL (VIDFIFOSIZE / 2) // MCLKs to burst fill video FIFO
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#define VID420FILL (VIDFIFOSIZE / 4) // 4:2:0 divides FIFO into two
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#define REF_XTAL (14318182ul) // Crystal reference frequency (Hz)
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#define TVO_XTAL (27000000ul) // TV-Out reference freq.
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typedef struct BWREGS_
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{
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BYTE MISCOutput; // 0x0080
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BYTE VCLK3Denom; // 0x0084
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BYTE VCLK3Num; // 0x0088
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WORD DispThrsTiming; // 0x00EA
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WORD GfVdFormat; // 0x00C0
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WORD RIFControl; // 0x0200
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BYTE BCLK_Mult; // 0x02C0
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BYTE BCLK_Denom; // 0x02C1
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WORD Control2; // 0x0418
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BYTE CR1; // 0x4 Get Screen Width from these registers
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BYTE CR1E; // 0x78
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}BWREGS, FAR *LPBWREGS;
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#ifdef WINNT_VER40
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// Be sure to synchronize the following structures with the one
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// in i386\Laguna.inc!
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//
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typedef struct PROGREGS_
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{
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WORD VW0_FIFO_THRSH;
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WORD DispThrsTiming;
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}PROGREGS, FAR *LPPROGREGS;
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#else
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typedef struct PROGREGS_
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{
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WORD VW0_FIFO_THRSH;
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WORD DispThrsTiming;
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}PROGREGS, FAR *LPPROGREGS;
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#endif
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static int ScaleMultiply(DWORD, DWORD, LPDWORD);
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DWORD ChipCalcTileWidth(LPBWREGS);
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BOOL ChipCalcMCLK(LPBWREGS, LPDWORD);
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BOOL ChipCalcVCLK(LPBWREGS, LPDWORD);
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BOOL ChipGetMCLK
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(
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#ifdef WINNT_VER40
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PDEV *,
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#endif
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LPDWORD
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);
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BOOL ChipGetVCLK
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(
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#ifdef WINNT_VER40
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PDEV *,
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#endif
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LPDWORD
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);
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BOOL ChipIsEnoughBandwidth(LPPROGREGS, LPVIDCONFIG, LPBWREGS);
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#endif // _5465BW_H
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#endif // WINNT_VER35
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