183 lines
4.6 KiB
C
183 lines
4.6 KiB
C
/******************************************************************************\
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* *
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* EN_FPGA.C - FPGA support. *
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* *
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* Copyright (c) C-Cube Microsystems 1996 *
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* All Rights Reserved. *
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* *
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* Use of C-Cube Microsystems code is governed by terms and conditions *
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* stated in the accompanying licensing statement. *
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* *
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\******************************************************************************/
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#ifdef VTOOLSD
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#include <vtoolsc.h>
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#include "monovxd.h"
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#else
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#include "Headers.h"
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#pragma hdrstop
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#endif
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#include "fpga.h"
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#include "boardio.h"
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//-------------------------------------------------------------------
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// GLOBAL VARIABLES DECLARATION
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//-------------------------------------------------------------------
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DWORD gdwFPGABase = 0;
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WORD gwShadow = 0;
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//-------------------------------------------------------------------
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// STATIC FUNCTIONS DECLARATION
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//-------------------------------------------------------------------
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/////////////////////////////////////////////////////////////////////
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// FPGA_Init
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//
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/////////////////////////////////////////////////////////////////////
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BOOL FPGA_Init( DWORD dwFPGABase )
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{
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//BYTE byFPGA; // FPGA shadow register
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MonoOutStr( " ÇÄ FPGA_Init " );
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MonoOutHex( dwFPGABase );
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gdwFPGABase = dwFPGABase;
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// Enable Ziva, CP, Audio DAC
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// FPGA_Write(0x83);
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// Bypass Decryption Device for now...
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// FPGA_Clear( FPGA_DECRIPTION_BYPASS|FPGA_SECTOR_START );
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#if 0
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#ifdef TC6807AF
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FPGA_Set( FPGA_BUS_MASTER );
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#else
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FPGA_Set( FPGA_BUS_MASTER | FPGA_DECRIPTION_BYPASS );
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#endif // TC6807AF
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#endif
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MonoOutStr( " Ķ " );
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return TRUE;
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}
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void FPGA_Set( WORD wMask )
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{
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//BYTE byFPGA;
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if ( !gdwFPGABase )
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return;
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//MonoOutStr( "<<< Set FPGA " );
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gwShadow |= wMask;
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//MonoOutHex( wMask );
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//MonoOutStr( "/" );
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//MonoOutHex( gwShadow );
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if ( wMask & 0x00FF )
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{
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/*
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byFPGA = BRD_ReadByte( gdwFPGABase );
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// Clean read-status/write-control bits
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byFPGA &= ~(ZIVA_INT|BGNI_ON);
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BRD_WriteByte( gdwFPGABase, (BYTE)(byFPGA | LOBYTE(wMask)) );
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MonoOutStr( "0: " );
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//MonoOutHex( BRD_ReadByte( gdwFPGABase ) );
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MonoOutHex( byFPGA | LOBYTE(wMask) );
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*/
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BRD_WriteByte( gdwFPGABase, LOBYTE(gwShadow) );
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}
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if ( wMask & 0xFF00 )
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{
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/*
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byFPGA = BRD_ReadByte( gdwFPGABase );
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BRD_WriteByte( gdwFPGABase, (BYTE)(byFPGA | HIBYTE(wMask)) );
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MonoOutStr( "1: " );
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//MonoOutHex( BRD_ReadByte( gdwFPGABase+1 ) );
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MonoOutHex( byFPGA | HIBYTE(wMask) );
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*/
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BRD_WriteByte( gdwFPGABase, HIBYTE(gwShadow) );
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}
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//MonoOutStr( " >>>" );
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}
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// Clear certain bit in the control register
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void FPGA_Clear( WORD wMask )
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{
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//BYTE byFPGA;
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if ( !gdwFPGABase )
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return;
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//MonoOutStr( "<<< Clear FPGA:" );
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gwShadow &= ~wMask;
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//MonoOutHex( wMask );
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//MonoOutStr( "/" );
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//MonoOutHex( gwShadow );
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if ( wMask & 0x00FF )
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{
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/*
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byFPGA = BRD_ReadByte( gdwFPGABase );
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// Clean read-status/write-control bits
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byFPGA &= ~(ZIVA_INT|BGNI_ON);
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BRD_WriteByte( gdwFPGABase, (BYTE)(byFPGA & ~LOBYTE(wMask)) );
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MonoOutStr( "0: " );
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//MonoOutHex( BRD_ReadByte( gdwFPGABase ) );
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MonoOutHex( byFPGA & ~LOBYTE(wMask) );
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*/
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BRD_WriteByte( gdwFPGABase, LOBYTE(gwShadow) );
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}
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if ( wMask & 0xFF00 )
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{
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/*
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byFPGA = BRD_ReadByte( gdwFPGABase );
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BRD_WriteByte( gdwFPGABase, (BYTE)(byFPGA & ~HIBYTE(wMask)) );
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MonoOutStr( "1: " );
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//MonoOutHex( BRD_ReadByte( gdwFPGABase+1 ) );
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MonoOutHex( byFPGA & ~HIBYTE(wMask) );
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*/
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BRD_WriteByte( gdwFPGABase, HIBYTE(gwShadow) );
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}
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//MonoOutStr( " >>>" );
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}
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void FPGA_Write( WORD wData )
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{
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//MonoOutStr( "<<< FPGA_Write " );
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if ( !gdwFPGABase )
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return;
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gwShadow = wData;
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BRD_WriteByte( gdwFPGABase, (BYTE)wData );
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//MonoOutStr( "0: " );
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//MonoOutHex( BRD_ReadByte( gdwFPGABase ) );
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//MonoOutHex( wData );
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//MonoOutStr( " >>>" );
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}
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WORD FPGA_Read()
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{
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if ( !gdwFPGABase )
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return 0;
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return BRD_ReadByte( gdwFPGABase );
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}
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